[WHY & HOW]
Enable ODM Combine + Fullscreen MPO on DCN2.1
For lower power consumption in video use cases.
Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Signed-off-by: NSung Lee <sung.lee@amd.com>
Acked-by: NAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why&How]
Create a separate dcn21_fast_validate_bw function for dcn21.
Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: NAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[WHY]
DF PState and Voltage State are coupled such that one cannot be
raised without raising the other. This uses more power than
is necessary in high bandwidth scenarios.

[HOW]
Add logic to create a new bounding box state that allows for
DF PState to be low while Voltage State is high. Watermarks
vlevel calculation logic was also udpated to assume
state 1 contains the new optimized state.
Signed-off-by: NSung Lee <sung.lee@amd.com>
Acked-by: NAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
get_pixel_clk_frequency_100hz is undefined in clock_source_funcs.

[how]
set function pointer: ".get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz"
Signed-off-by: NDavid Galiffi <David.Galiffi@amd.com>
Reviewed-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: NAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

	dm_comressor_info -> dm_compressor_info

The kernel-doc markup is right, but the struct itself
and their references contain a typo.
Signed-off-by: NMauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Enable Memory Access at Last Level (MALL) feature for display.

v2: squash in 64 bit division fixes
Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

A break is not needed if it is preceded by a return or break
Reviewed-by: NHarry Wentland <harry.wentland@amd.com>
Acked-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NTom Rix <trix@redhat.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Screen corruption on Navi10 card

[How]
Set system context in DCN only on Renoir
Tested-by: NMatt Coffin <mcoffin13@gmail.com>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NYifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: NRoman Li <Roman.Li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

As far a I can tell uses a variant of DCN3xx which uses num_pkrs.

If we do not initialize the variable we will set the register field
to ilog2(0) = -1, though the mask will reduce that to 7. Pretty sure
7 is not the value we want here.
Signed-off-by: NBas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: NMarek Olšák <marek.olsak@amd.com>
Reviewed-and-Tested-by: NHuang Rui <ray.huang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Some setups will fail to build. So copy dcn301 makefile setup
which is known to work
Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

On connector destruction call drm_dp_mst_topology_mgr_destroy
to release resources allocated in drm_dp_mst_topology_mgr_init.
Do it only if MST manager was initilized before otherwsie a crash
is seen on driver unload/device unplug.
Reviewed-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: NAndrey Grodzovsky <andrey.grodzovsky@amd.com>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This fixes regression on device unplug and/or driver unload.

[   65.681501 <    0.000004>] BUG: kernel NULL pointer dereference, address: 0000000000000008
[   65.681504 <    0.000003>] #PF: supervisor write access in kernel mode
[   65.681506 <    0.000002>] #PF: error_code(0x0002) - not-present page
[   65.681507 <    0.000001>] PGD 7c9437067 P4D 7c9437067 PUD 7c9db7067 PMD 0
[   65.681511 <    0.000004>] Oops: 0002 [#1] SMP NOPTI
[   65.681512 <    0.000001>] CPU: 8 PID: 127 Comm: kworker/8:1 Tainted: G        W  O      5.9.0-rc2-dev+ #59
[   65.681514 <    0.000002>] Hardware name: System manufacturer System Product Name/PRIME X470-PRO, BIOS 4406 02/28/2019
[   65.681525 <    0.000011>] Workqueue: events drm_connector_free_work_fn [drm]
[   65.681535 <    0.000010>] RIP: 0010:drm_atomic_private_obj_fini+0x11/0x60 [drm]
[   65.681537 <    0.000002>] Code: de 4c 89 e7 e8 70 f2 ba f8 48 8d 65 d8 5b 41 5c 41 5d 41 5e 41 5f 5d c3 90 0f 1f 44 00 00 48 8b 47 08 48 8b 17 55 48 89 e5 53 <48> 89 42 08 48 89 10 48 b8 00 01 00 00 00 00 ad de 48 89 fb 48 89
[   65.681541 <    0.000004>] RSP: 0018:ffffa5fa805efdd8 EFLAGS: 00010246
[   65.681542 <    0.000001>] RAX: 0000000000000000 RBX: ffff9a4b094654d8 RCX: 0000000000000000
[   65.681544 <    0.000002>] RDX: 0000000000000000 RSI: ffffffffba197bc2 RDI: ffff9a4b094654d8
[   65.681545 <    0.000001>] RBP: ffffa5fa805efde0 R08: ffffffffba197b82 R09: 0000000000000040
[   65.681547 <    0.000002>] R10: ffffa5fa805efdc8 R11: 000000000000007f R12: ffff9a4b09465888
[   65.681549 <    0.000002>] R13: ffff9a4b36f20010 R14: ffff9a4b36f20290 R15: ffff9a4b3a692840
[   65.681551 <    0.000002>] FS:  0000000000000000(0000) GS:ffff9a4b3ea00000(0000) knlGS:0000000000000000
[   65.681553 <    0.000002>] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[   65.681554 <    0.000001>] CR2: 0000000000000008 CR3: 00000007c9c82000 CR4: 00000000003506e0
[   65.681556 <    0.000002>] Call Trace:
[   65.681561 <    0.000005>]  drm_dp_mst_topology_mgr_destroy+0xc4/0xe0 [drm_kms_helper]
[   65.681612 <    0.000051>]  amdgpu_dm_connector_destroy+0x3d/0x110 [amdgpu]
[   65.681622 <    0.000010>]  drm_connector_free_work_fn+0x78/0x90 [drm]
[   65.681624 <    0.000002>]  process_one_work+0x164/0x410
[   65.681626 <    0.000002>]  worker_thread+0x4d/0x450
[   65.681628 <    0.000002>]  ? rescuer_thread+0x390/0x390
[   65.681630 <    0.000002>]  kthread+0x10a/0x140
[   65.681632 <    0.000002>]  ? kthread_unpark+0x70/0x70
[   65.681634 <    0.000002>]  ret_from_fork+0x22/0x30

This reverts commit 1545fbf9.
Signed-off-by: NAndrey Grodzovsky <andrey.grodzovsky@amd.com>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

DCN301 needs to use dmub create abm instance instead of dce.

[ 1138.854204] BUG: kernel NULL pointer dereference, address: 0000000000000000
[ 1138.854206] #PF: supervisor instruction fetch in kernel mode
[ 1138.854207] #PF: error_code(0x0010) - not-present page
[ 1138.854208] PGD 0 P4D 0
[ 1138.854212] Oops: 0010 [#1] SMP NOPTI
[ 1138.854216] CPU: 6 PID: 1240 Comm: modprobe Tainted: G        W  OE     5.9.0-rc2-custom #1
[ 1138.854217] Hardware name: AMD Chachani-VN/Chachani-VN, BIOS BAerithA104 10/01/2020
[ 1138.854221] RIP: 0010:0x0
[ 1138.854224] Code: Bad RIP value.
[ 1138.854226] RSP: 0018:ffffc90001c4f638 EFLAGS: 00010286
[ 1138.854228] RAX: 0000000000000000 RBX: ffff88804f2b2800 RCX: ffffc90001c4f740
[ 1138.854229] RDX: 00000000000000e8 RSI: ffffc90001c4f640 RDI: ffff88805816f300
[ 1138.854230] RBP: ffffc90001c4f850 R08: ffffc90001c4f644 R09: ffffc90001c4f654
[ 1138.854231] R10: ffffc90001c4f72c R11: ffffc90001c4f740 R12: ffffc90001c4f640
[ 1138.854232] R13: ffffc90001c4f728 R14: 0000000000000000 R15: ffff888007296381
[ 1138.854235] FS:  00007f5f44d84540(0000) GS:ffff88805e380000(0000) knlGS:0000000000000000
[ 1138.854236] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[ 1138.854237] CR2: ffffffffffffffd6 CR3: 00000000194f4000 CR4: 0000000000050ee0
[ 1138.854239] Call Trace:
[ 1138.854447]  dmub_init_abm_config+0x220/0x267 [amdgpu]
[ 1138.854654]  dm_late_init+0x197/0x1ad [amdgpu]
[ 1138.854846]  ? dm_late_init+0x197/0x1ad [amdgpu]
[ 1138.854999]  amdgpu_device_ip_late_init+0x6f/0x21b [amdgpu]
[ 1138.855148]  amdgpu_device_init+0x1b7f/0x1cfb [amdgpu]
[ 1138.855293]  amdgpu_driver_load_kms+0x2c/0x26e [amdgpu]
[ 1138.855437]  amdgpu_pci_probe+0x1c7/0x249 [amdgpu]
[ 1138.920489]  local_pci_probe+0x48/0x80
[ 1138.920492]  pci_device_probe+0x10f/0x1c0
Signed-off-by: NHuang Rui <ray.huang@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
display S/G mode fails in Renoir

[how]
Setup system context in dm init.
Signed-off-by: NYifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Fix this to avoid build problems if DRM_AMD_DC_DCN3_02 is defined, but
DRM_AMD_DC_DCN3_01 is not.

Fixes: 36d26912 ("drm/amd/display: Add support for DCN302 (v2)")
Acked-by: NNirmoy Das <nirmoy.das@amd.com>
Acked-by: NRandy Dunlap <rdunlap@infradead.org>
Reported-by: NRandy Dunlap <rdunlap@infradead.org>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

As warned when running "make htmldocs":

	./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:345: warning: Function parameter or member 'force_timing_sync' not described in 'amdgpu_display_manager'

This new struct member was not documented at kernel-doc markup.

Fixes: 3d4e52d0 ("drm/amd/display: Add debugfs for forcing stream timing sync")
Signed-off-by: NMauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Functions (disable_all_writeback_pipes_for_stream &
dc_enable_stereo & dc_post_update_surfaces_to_stream)
always return true, there is no need to keep the return value.
This change is to make the code a bit more readable.
Signed-off-by: NBernard Zhao <bernard@vivo.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Display Manager support for green_sardine
Signed-off-by: NRoman Li <Roman.Li@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Display Core support for green_sardine
Signed-off-by: NRoman Li <Roman.Li@amd.com>
Acked-by: NHersen Wu <hersenxs.wu@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Handle CAVE_DIMGREY_CAVEFISH in amdgpu_dm

v2: fix rebase typo (Alex)
Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

 - add DCN302 resource, irq service, dmub loader,
 - handle  DC_VERSION_DCN_3_02
 - define DCN302 power gating functions
 - handle DCN302 in GPIO files
 - define I2C regs
 - add CONFIG_DRM_AMD_DC_DCN3_02 guard

v2: rebase fixes (Alex)
Signed-off-by: NJoshua Aberback <joshua.aberback@amd.com>
Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

It was recently introduced a change that enables driver to disable
streams if pixel clock changes. Consequently, the code path executed in
the disable vbios function expanded to an encoder verification part.
The encoder loop is nested inside the pipe count loop, and both loops
share the 'i' variable in control of their flow. This situation may lead
to an infinite loop because the encoder loop constantly updates the `i`
variable, making the first loop always positive. As a result, we can see
a soft hang during the module load (modprobe amdgpu) and a series of
dmesg log that looks like this:

kernel:[  124.538727] watchdog: BUG: soft lockup - CPU#2 stuck for 22s!
[modprobe:1000]

RSP: 0018:ffffabbf419bf0e8 EFLAGS: 00000282
RAX: ffffffffc0809de0 RBX: ffff93b35ccc0000 RCX: ffff93b366c21800
RDX: 0000000000000000 RSI: 0000000000000141 RDI: ffff93b35ccc0000
RBP: ffffabbf419bf108 R08: ffffabbf419bf164 R09: 0000000000000001
R10: 0000000000000003 R11: 0000000000000003 R12: 0000000008677d40
R13: 0000000000000141 R14: ffff93b35cfc0000 R15: ffff93b35abc0000
FS:  00007f1400717540(0000) GS:ffff93b37f680000(0000)
     knlGS:0000000000000000
CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
CR2: 00005649b66b0968 CR3: 00000003e0fec000 CR4: 0000000000350ee0
Call Trace:
 amdgpu_device_rreg+0x17/0x20 [amdgpu]
 amdgpu_cgs_read_register+0x14/0x20 [amdgpu]
 dm_read_reg_func+0x3a/0xb0 [amdgpu]
 get_pixel_clk_frequency_100hz+0x30/0x50 [amdgpu]
 dc_commit_state+0x8f1/0xae0 [amdgpu]
 ? drm_calc_timestamping_constants+0x101/0x160 [drm]
 amdgpu_dm_atomic_commit_tail+0x39d/0x21a0 [amdgpu]
 ? dcn21_validate_bandwidth+0xe5/0x290 [amdgpu]
 ? kfree+0xc3/0x390
 ? dcn21_validate_bandwidth+0xe5/0x290 [amdgpu]
...
RSP: 002b:00007fff26009bd8 EFLAGS: 00000246 ORIG_RAX: 0000000000000139
RAX: ffffffffffffffda RBX: 000055a8025bea50 RCX: 00007f140085c89d
RDX: 0000000000000000 RSI: 000055a8025b8290 RDI: 000000000000000c
RBP: 0000000000040000 R08: 0000000000000000 R09: 0000000000000000
R10: 000000000000000c R11: 0000000000000246 R12: 000055a8025b8290
R13: 0000000000000000 R14: 000055a8025bead0 R15: 000055a8025bea50

This issue was fixed by introducing a second variable for the internal
loop.

Fixes: 8353d30e ("drm/amd/display: disable stream if pixel clock changed with link active")
Reviewed-by: NRoman Li <Roman.Li@amd.com>
Reviewed-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

These function pointers are missing from dcn30_init

.calc_vupdate_position : Used to help avoid cursor stuttering
.set_pipe : Needed for setting ABM

So add them
Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

These were leftover from the initial implementation, but
never used.  Drop them.
Reviewed-by: NEvan Quan <evan.quan@amd.com>
Noticed-by: NRyan Taylor <ryan.taylor@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAric Cyr <aric.cyr@amd.com>
Acked-by: NEryk Brol <eryk.brol@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAnthony Koo <Anthony.Koo@amd.com>
Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NEryk Brol <eryk.brol@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
DAL resume from BACO time is longer if we always flush inst_fb

[How]
Check if backdoor loading to flush inst_fb
Signed-off-by: NAlvin Lee <alvin.lee2@amd.com>
Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: NEryk Brol <eryk.brol@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
When forcing 3D mode in DAL, we set the right address to be the same as the
left address. We need to do the same for the meta addresses.

[How]
Program right meta to be same as left meta.
Signed-off-by: NAlvin Lee <alvin.lee2@amd.com>
Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NEryk Brol <eryk.brol@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[WHY]
Currently construction of clock limits gets skipped for diags.
This logic would be useful to get tested in diags.

[HOW]
Copy existing states to clk_table such that update_bw_bounding_box
logic gets used to fill the table.
Signed-off-by: NSung Lee <sung.lee@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NEryk Brol <eryk.brol@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
On narrow range monitors without LFC, a margin prevents good utilization
of the available range.

[How]
Decrease the margin for exiting fixed mode and fix the frame counter to
reset if a non-consecutive render is found.
Signed-off-by: NAric Cyr <aric.cyr@amd.com>
Reviewed-by: NAnthony Koo <Anthony.Koo@amd.com>
Acked-by: NEryk Brol <eryk.brol@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This should be programmed with timing rather than with odm.
Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: NEryk Brol <eryk.brol@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
HDCP 1.4 failed on SL8800 SW w/a test driver use.

[how]
Slow down the HW i2c speed when used by HW i2c.
This request: each acquired_i2c_engine setup the i2c speed needed
and sets the I2c engine for HDCP use at release_engine.

This covers SW using HW i2c engine and HDCP using HW i2c engine.
for dmcu using HW i2c engine, needs add similar logic in dmcu fw.
Signed-off-by: NCharlene Liu <Charlene.Liu@amd.com>
Reviewed-by: NChris Park <Chris.Park@amd.com>
Acked-by: NEryk Brol <eryk.brol@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
enable ODM on eDP panel with ABM will result in color difference
on the panel due to only one ABM module to set one pipe.

[How]
Block ABM in case of ODM enabled on eDP.
Signed-off-by: NYongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: NEric Yang <eric.yang2@amd.com>
Acked-by: NEryk Brol <eryk.brol@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
When we transfer the WM range table to SMU, they can perform a watermark
switch right away. This can be a problem if we're in not in accelerated mode
during hw_init as SMU may initiate a dummy p-state change before the rest
of the watermarks are programmed. Watermark set A is defined to be
sufficient for all cases, so we can copy the values from set A to all other
sets, avoiding any issues from SMU doing WM switches.

[How]
 - new hubbub func init_watermarks
 - copy register values from set A to all other sets
 - call init_watermarks before calling notify_wm_ranges
Signed-off-by: NJoshua Aberback <joshua.aberback@amd.com>
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NEryk Brol <eryk.brol@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
During driver unload, it is expected that p-state switching is supported.
If it's not supported, PMFW will hang due to a forced p-state switch. Even
if the current timing does not support p-state normally, we still want to
force allow because the worst that can happen is underflow. This will
match Navi10 behaviour.

[How]
 - new hubbub func to control the force pstate register
 - force allow when releasing display ownership
   - registers are inaccessible after due to m_cgs.hwNotAvailable
 - explicitly disable force signal during hw_init
   - if driver is disabled and re-enabled, register not cleared otherwise

Also, remove DCN3 part of dcn10_init_hw, we will not be going back to it.
Signed-off-by: NJoshua Aberback <joshua.aberback@amd.com>
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NEryk Brol <eryk.brol@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[WHY]
This change was implemented because the comment style was not uniform
across the file. In some lines comments were initiated with // and in
others they were in between /* ... */.
Additionally, the style for multi-line comments was also not uniform and
some comment lines were missing the space between the opening /* and the
first word of the comment.

[HOW]
All comments are now in between /*.../*, multi line comments also use
/*...*/ and for every comment there is now a space between the opening
/* and the first word of the comment.
Signed-off-by: NFelipe <Felipe.Clark@amd.com>
Acked-by: NEryk Brol <eryk.brol@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
When running games or benchmarking with v-sync disabled, disabling
a plane (which is v-sync) can cause underflow. This is caused by
flips pending before pipe locking being applied after locks are
released and pipes could have been re-arranged or disconnected. This
could potentially apply a flip on incorrect pipe. Also, previous logic
of always locking pipes was unnecessary.

[How]
Only lock the pipes when there is a pipe being disabled to increase
efficiency. Before the pipes are locked, check that any pending flips
are cleared to ensure the flips are applied to the correct pipe.
Signed-off-by: NAric Cyr <aric.cyr@amd.com>
Acked-by: NEryk Brol <eryk.brol@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
We will hang if we report switch in VACTIVE but not in VBLANK and DPG_EN = 1

[How]
Block switch in ACTIVE if not supported in BLANK
Signed-off-by: NAlvin Lee <alvin.lee2@amd.com>
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NEryk Brol <eryk.brol@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAric Cyr <aric.cyr@amd.com>
Acked-by: NEryk Brol <eryk.brol@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>