This patch adds a fake Qualcomm ID 0x00051180 to the amba_ids, as Qualcomm
SDCC controller is pl180, but amba id registers read 0x0's.
The plan is to remove SDCC driver totally and use mmci as the main SD
controller driver for Qualcomm SOCs.
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

MCIFIFOCNT register behaviour on Qcom chips is very different than the other
pl180 integrations. MCIFIFOCNT register contains the number of
words that are still waiting to be transferred through the FIFO. It keeps
decrementing once the host CPU reads the MCIFIFO. With the existing logic and
the MCIFIFOCNT behaviour, mmci_pio_read will loop forever, as the FIFOCNT
register will always return transfer size before reading the FIFO.

Also the data sheet states that "This register is only useful for debug
purposes and should not be used for normal operation since it does not reflect
data which may or may not be in the pipeline".

This patch implements a qcom specific get_rx_fifocnt function which is
implemented based on status register flags. Based on qcom_fifo flag in
variant data structure, the corresponding get_rx_fifocnt function is selected.
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

On Controllers like Qcom SD card controller where cclk is mclk and mclk should
be directly controlled by the driver.

This patch adds support to control mclk directly in the driver, and also
adds explicit_mclk_control flag in variant structure giving more flexibility
to the driver.
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
[Ulf Hansson] Fixed checkpatch warning
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Some of the controller have maximum supported frequency, This patch adds
support in variant data structure to specify such restrictions. This
gives more flexibility in calculating the f_max before passing it to
mmc-core.
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

On some SOCs like Qcom there are explicit bits in the command register
to specify if its a data transfer command or not. So this patch adds
support to such bits in variant data, giving more flexibility to the
driver.
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

This patch adds edge support for data and command out to variant structure
giving more flexibility to the driver to support more SOCs which have
different clock register layout.

Without this patch other new SOCs like Qcom will have to add more code to
special case them
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
[Ulf Hansson] Resolved conflict
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

This patch adds 8bit bus enable to variant structure giving more flexibility
to the driver to support more SOCs which have different clock register layout.

Without this patch other new SOCs like Qcom will have to add more code
to special case them.
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
[Ulf Hansson] Resolved conflict
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

This patch adds ddrmode mask to variant structure giving more flexibility
to the driver to support more SOCs which have different datactrl register
layout.

Without this patch datactrl register is updated with incorrect ddrmode mask,
resulting in failures on Qualcomm SD Card Controller.
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
[Ulf Hansson] Resolved conflict
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Instance of this IP on Qualcomm's SOCs has bit different layout for datactrl
register. Bit position datactrl[16:4] hold the true block size instead of power
of 2.
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

On Qcom SD Card controller POWER, CLKCTRL, DATACTRL and COMMAND registers
should be updated in MCLK domain, and writes to these registers must be
separated by three MCLK cycles. This resitriction is not applicable for
other registers. Any subsequent writes to these register will be ignored
until 3 MCLK have passed.

One usec delay between two CMD register writes is not sufficient in the
card identification phase where the CCLK is very low. This patch replaces
a static 1 usec delay to use mmci_reg_delay function which can provide
correct delay depending on the cclk frequency.

Without this patch the card is not detected.
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

This patch adds a Qualcomm SD Card controller specific register variations
to header file. Qualcomm SDCC controller is pl180, with slight changes in
the register layout from standard pl180 register set.
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

This patch replaces a constant used in calculating timeout with a proper
macro. This is make code more readable.
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

We have a number of front-end drivers for SDHCI_PLTFM, some of them
use 'select MMC_SDHCI_PLTFM', others use 'depends on'. This is
inconsistent and confusing, and in one case has also led to a
build error because of incomplete dependencies:

warning: (MMC_SDHCI_PXAV3 && MMC_SDHCI_PXAV2 && MMC_SDHCI_BCM_KONA) selects MMC_SDHCI_PLTFM which has unmet direct dependencies (MMC && MMC_SDHCI)
drivers/built-in.o: In function `sdhci_sirf_resume':
:(.text+0xaaacb4): undefined reference to `sdhci_resume_host'
drivers/built-in.o: In function `sdhci_sirf_suspend':
:(.text+0xaaacf8): undefined reference to `sdhci_suspend_host'
drivers/built-in.o: In function `sdhci_sirf_probe':
:(.text+0xaaaf44): undefined reference to `sdhci_add_host'
:(.text+0xaaaf50): undefined reference to `sdhci_remove_host'

This changes Kconfig to use 'depends on MMC_SDHCI_PLTFM' for all these
cases, to fix the build error and make the logic more logical.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

The MMC host driver should not select the pmic driver, since that
may have other dependencies, notably i2c in this case. It's not
clear what the exact requirement of the driver is, but to preserve
the behavior, this patch changes the 'select' into 'depends on',
meaning you now have to turn on TPS65010 explicitly and then
MMC_OMAP.

Found during randconfig build testing.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Cc: linux-omap@vger.kernel.org
Cc: Jarkko Nikula <jarkko.nikula@bitmer.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

gcc correctly points out that hw_state can be used uninitially
in the mvsd_setup_data() function. This rearranges the function
to ensure it always contains a proper value.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Cc: Nicolas Pitre <nico@fluxnic.net>
Cc: Chris Ball <chris@printf.net>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: linux-mmc@vger.kernel.org
Acked-by: NNicolas Pitre <nico@linaro.org>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

This avoids a build error due to the use of flush_dcache_page.

drivers/mmc/host/atmel-mci.c: In function 'atmci_read_data_pio':
drivers/mmc/host/atmel-mci.c:1870:5: error: implicit declaration of function 'flush_dcache_page' [-Werror=implicit-function-declaration]
     flush_dcache_page(sg_page(sg));
     ^
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Cc: Ludovic Desroches <ludovic.desroches@atmel.com>
Acked-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

The sdhci core was refactored recently and some of those
refactorings required changes in every sdhci platform driver.
Those updates happened around the same time as when the msm
driver was merged so the refactorings missed the msm driver.
Hook in the basic library functions so that we can boot apq8074
dragonboards again instead of crashing when we try to jump to
NULL function pointers.
Reported-by: NKevin Hilman <khilman@linaro.org>
Cc: Georgi Djakov <gdjakov@mm-sol.com>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Acked-by: NKumar Gala <galak@codeaurora.org>
Reviewed-by: NGeorgi Djakov <gdjakov@mm-sol.com>
Tested-by: NKevin Hilman <khilman@linaro.org>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Fix a number of wrong print formats.
Signed-off-by: NGuennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Fix the compile error.
(Removed the card_tasklet at "mmc: sdhci: push card_tasklet into treaded irq handler")

drivers/mmc/host/sdhci-s3c.c: In function ‘sdhci_s3c_notify_change’:
drivers/mmc/host/sdhci-s3c.c:402:25: error: ‘struct sdhci_host’ has no member named ‘card_tasklet’
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NChris Ball <chris@printf.net>

The Allwinner sunxi mmc host uses dma in bus-master mode using a built-in
designware idmac controller, which is identical to the one found in the mmc-dw
hosts. However the rest of the host is not identical to mmc-dw, it deals with
sending stop commands in hardware which makes it significantly different
from the mmc-dw devices.
Signed-off-by: NDavid Lanzendörfer <david.lanzendoerfer@o2s.ch>
[hdegoede@redhat.com: various cleanups and fixes]
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
Acked-by: NChris Ball <chris@printf.net>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch adds a driver for the Renesas usdhi6rol0 SD/SDIO host controller
in both PIO and DMA modes.
Signed-off-by: NGuennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
Signed-off-by: NChris Ball <chris@printf.net>

Remove the option to provide DMA configuration as platform data,
enforce it through DT.
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Roland Stigge <stigge@antcom.de>
Acked-by: NArnd Bergmann <arnd@arndb.de>

The commit below introduced compile errors, let's fix them.
mmc: sdhci-of-esdhc: remove platform_suspend/platform_resume callbacks

Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NChris Ball <chris@printf.net>

Tegra SDHCI controllers, by default, report a base clock frequency of
208Mhz in SDHCI_CAPABILTIES which may or may not be equal to the actual
base clock frequency.  This is because the clock rate is configured by
the clock controller, which is external to the SD/MMC controller.  Since
the SD/MMC controller has no knowledge of how this clock is configured,
it will simply report the maximum frequency.  While the reported value
can be overridden by setting BASE_CLK_FREQ in VENDOR_CLOCK_CTRL on
Tegra30 and later SoCs, just set CAP_CLOCK_BASE_BROKEN and supply
sdhci_pltfm_clk_get_max_clock(), which simply does a clk_get_rate(),
as the get_max_clock() callback.
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Tested-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NChris Ball <chris@printf.net>

Program TEGRA_SDHCI_VENDOR_MISC_CTRL so that UHS modes aren't advertised
in SDHCI_CAPABILITIES_1.  While the Tegra SDHCI controller does support
these modes, they require Tegra-specific tuning and calibration routines
which the driver does not support yet.
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Tested-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NChris Ball <chris@printf.net>

f8ec589b ("mmc: sdhci-dove: allow GPIOs to be used for card detection
on Dove" added a gpio based card detect interrupt handler that was hooked
up into card_tasket.

3560db8e ("mmc: sdhci: push card_tasklet into threaded irq handler")
now removed that very card_tasklet causing sdhci-dove to fail on build
with:
drivers/mmc/host/sdhci-dove.c: In function 'sdhci_dove_carddetect_irq':
drivers/mmc/host/sdhci-dove.c:42:24: error: 'struct sdhci_host' has no member named 'card_tasklet'

To fix both the build error and get a working gpio card detection without
card_tasklet, replace sdhci_get_of_property() with more recent
mmc_of_parse(). It takes care of gpio-based card detect passed through DT
already and allows to remove the offending code sections dealing with
removed card_tasklet.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NChris Ball <chris@printf.net>

DT-enabled Dove moved over from ARCH_DOVE in mach-dove to MACH_DOVE in
mach-mvebu. As non-DT ARCH_DOVE will stay to rot for a while, add a new
DT-only MACH_DOVE Kconfig. This slipped through the cracks and now is
a fix to allow to build Dove's SDHCI driver for mach-mvebu on v3.15-rc.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: NJason Cooper <jason@lakedaemon.net>
Tested-by: NAndrew Lunn <andrew@lunn.ch>
Tested-by: NRiku Voipio <riku.voipio@iki.fi>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NChris Ball <chris@printf.net>

The SD Host Controller spec states that the SD Host Controller can
request that the driver send up to 40 CMD19's while doing tuning
and that the total time the card spends responding must be < 150ms.
The sdhci_execute_tuning() function in sdhci.c that loops through
sending the CMD19's has multiple bugs. First it sets a "timeout"
variable to 150 and a loop counter variable to 40. It then decrements
both variables by 1 at the end of each loop. It tries to handle
violations of the count and time by doing a break when BOTH variables
are equal to zero, which can never happen because they we set to
different values and decremented by 1 at the same time. The timeout
variable is not based on time at all and is totally useless.
The routine also considers a loop counter of zero to be an error
which means that any controller that requests the max of 40 CMD19s
will cause tuning to fail and be disabled.

I've fixed these issues by allowing up to 40 CMD19's and I've removed
any attempt to handle the 150ms time limit. Removing timeout checking
seems safe here because each CMD19 is timeout protected and the max
loop counters insures we don't loop forever. Adding timeout checking
would not be as simple as snapping the time at the loop start and
checking for 150ms to pass because the loop queues the CMD19's and
uses events to wait for completion so the time would include
all the normal scheduler latencies.
Signed-off-by: NAl Cooper <alcooperx@gmail.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NChris Ball <chris@printf.net>

It's caused by the platform driver was still using MMC_TIMING_UHS_DDR50
for MMC DDR mode which needs update too.
Reported-by: NFabio Estevam <fabio.estevam@freescale.com>
Reported-by: NShawn Guo <shawn.guo@freescale.com>
Signed-off-by: NDong Aisheng <b29396@freescale.com>
Tested-by: NFabio Estevam <fabio.estevam@freescale.com>
[Ulf Hansson] Resolved conflict
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NChris Ball <chris@printf.net>

Add O2Micro/BayHubTech chip 8520 subversion B1 SD3.0 support.
Add O2Micro/BayHubTech chip 8620 and 8621 SD3.0 support
Enable Led function of 8520 chip.
Signed-off-by: NPeter Guo <peter.guo@bayhubtech.com>
Signed-off-by: NAdam Lee <adam.lee@canonical.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NChris Ball <chris@printf.net>

moving dmaengine consumer specific function to omap-dmaengine.h
to Resolve build failure seen with sh-allmodconfig:
    include/linux/omap-dma.h:171:8: error: expected identifier before numeric constant
    make[4]: *** [drivers/mmc/host/omap_hsmmc.o] Error 1

Cc: Russell King - ARM Linux <linux@arm.linux.org.uk>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: NBalaji T K <balajitk@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NChris Ball <chris@printf.net>

Check for set block count command fails always since host->cmd is set
to NULL in the same function incorrectly. Correct host->cmd usage properly.
Signed-off-by: NBalaji T K <balajitk@ti.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NChris Ball <chris@printf.net>

With devm_ioremap_resource conversion release_mem_region, iounmap can be
removed in clean up path
Signed-off-by: NBalaji T K <balajitk@ti.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NChris Ball <chris@printf.net>

With devm_request_threaded_irq conversion free_irq can be removed
in clean up path
Signed-off-by: NBalaji T K <balajitk@ti.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NChris Ball <chris@printf.net>

With devm_request_irq conversion free_irq can be removed in clean up path
Signed-off-by: NBalaji T K <balajitk@ti.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NChris Ball <chris@printf.net>

With devm_clk_get conversion clk_put can be removed in clean up path
Signed-off-by: NBalaji T K <balajitk@ti.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NChris Ball <chris@printf.net>

The Allwinner sunxi mmc host uses dma in bus-master mode using a built-in
designware idmac controller, which is identical to the one found in the
mmc-dw hosts. However the rest of the host is not identical to mmc-dw, it
deals with sending stop commands in hardware which makes it significantly
different from the mmc-dw devices.
Signed-off-by: NDavid Lanzendörfer <david.lanzendoerfer@o2s.ch>
[hdegoede@redhat.com: various cleanups and fixes]
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NChris Ball <chris@printf.net>

Signed-off-by: NAxel Lin <axel.lin@ingics.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NChris Ball <chris@printf.net>

Also uses NSEC_PER_SEC and USEC_PER_SEC instead of hard-coded value.
This makes the intention more clear.
Signed-off-by: NAxel Lin <axel.lin@ingics.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NChris Ball <chris@printf.net>

Data errors are completely expected during tuning.  Printing them out
is confusing people looking at the kernel logs.  They see things like:

 [    3.613296] dwmmc_exynos 12200000.dwmmc0: data error, status 0x00000088

...and they think something is wrong with their hardware.

Remove the printouts.  We'll leave it up to a higher level to report
about errors.
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Reviewed-by: NAlim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NChris Ball <chris@printf.net>