1. 25 2月, 2012 3 次提交
  2. 27 1月, 2012 6 次提交
    • J
      ARM: OMAP2+: arch/arm/mach-omap2/smartreflex.c: add missing iounmap · 14ea9601
      Julia Lawall 提交于
      Add missing iounmap in error handling code, in a case where the function
      already preforms iounmap on some other execution path.
      
      A simplified version of the semantic match that finds this problem is as
      follows: (http://coccinelle.lip6.fr/)
      
      // <smpl>
      @@
      expression e;
      statement S,S1;
      int ret;
      @@
      e = \(ioremap\|ioremap_nocache\)(...)
      ... when != iounmap(e)
      if (<+...e...+>) S
      ... when any
          when != iounmap(e)
      *if (...)
         { ... when != iounmap(e)
           return ...; }
      ... when any
      iounmap(e);
      // </smpl>
      Signed-off-by: NJulia Lawall <Julia.Lawall@lip6.fr>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      14ea9601
    • J
      ARM: OMAP2+: arch/arm/mach-omap2/devices.c: introduce missing kfree · e0feca89
      Julia Lawall 提交于
      pdata needs to be freed before leaving the function in an error case.
      
      A simplified version of the semantic match that finds the problem is as
      follows: (http://coccinelle.lip6.fr)
      
      // <smpl>
      @r exists@
      local idexpression x;
      statement S;
      identifier f1;
      position p1,p2;
      expression *ptr != NULL;
      @@
      
      x@p1 = \(kmalloc\|kzalloc\|kcalloc\)(...);
      ...
      if (x == NULL) S
      <... when != x
           when != if (...) { <+...x...+> }
      x->f1
      ...>
      (
       return \(0\|<+...x...+>\|ptr\);
      |
       return@p2 ...;
      )
      
      @script:python@
      p1 << r.p1;
      p2 << r.p2;
      @@
      
      print "* file: %s kmalloc %s return %s" % (p1[0].file,p1[0].line,p2[0].line)
      // </smpl>
      Signed-off-by: NJulia Lawall <julia@diku.dk>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      e0feca89
    • G
      ARM: OMAP: fix MMC2 loopback clock handling · d82e5190
      Grazvydas Ignotas 提交于
      Currently MMC2 setup code can only enable loopback clock and
      relies on reset value for boards that need to have it disabled.
      This causes a problem with certain bootloaders that always enable
      that clock, resulting with unwanted bootloader dependencies.
      
      Fix this by making it disable the clock if board data says so.
      Signed-off-by: NGrazvydas Ignotas <notasas@gmail.com>
      Acked-by: NIgor Grinberg <grinberg@compulab.co.il>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      d82e5190
    • G
      ARM: OMAP: fix erroneous mmc2 clock change on mmc3 setup · ffa1e4ed
      Grazvydas Ignotas 提交于
      hsmmc23_before_set_reg() can set MMCSDIO2ADPCLKISEL bit, which
      enables internal clock for MMC2. Currently this function is also called
      by code handling MMC3, and if .internal_clock is set in platform data
      (by default it currently is), it will set MMCSDIO2ADPCLKISEL for MMC2
      instead of MMC3 (MMC3 doesn't have such bit so nothing actually needs to
      be done). This breaks 2nd SD slot on pandora.
      
      Fix this by changing hsmmc23_before_set_reg() to only handle MMC2.
      Note that this removes .remux() call for MMC3, but no board currently
      needs it and it's also not called for MMC4 and MMC5.
      Signed-off-by: NGrazvydas Ignotas <notasas@gmail.com>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      ffa1e4ed
    • Y
      ARM: OMAP2+: GPMC: fix device size setup · 8ef5d844
      Yegor Yefremov 提交于
      following statement can only change device size from 8-bit(0) to 16-bit(1),
      but not vice versa:
      
      regval |= GPMC_CONFIG1_DEVICESIZE(wval);
      
      so as this field has 1 reserved bit, that could be used in future,
      just clear both bits and then OR with the desired value
      Signed-off-by: NYegor Yefremov <yegorslists@googlemail.com>
      Cc: stable@vger.kernel.org
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      8ef5d844
    • V
      ARM: OMAP2+: timer: Fix crash due to wrong arg to __omap_dm_timer_read_counter · dbc3982a
      Vaibhav Hiremath 提交于
      Commit 2f0778af (ARM: 7205/2: sched_clock: allow sched_clock to be
      selected at runtime) had a typo for the case when CONFIG_OMAP_32K_TIMER
      is not set.
      
      In dmtimer_read_sched_clock(), wrong argument was getting passed to
      __omap_dm_timer_read_counter() function call; instead of "&clksrc",
      we were passing "clksrc.io_base", which results into kernel crash.
      
      To reproduce kernel crash, just disable the CONFIG_OMAP_32K_TIMER config
      option (and DEBUG_LL) and build/boot the kernel.
      This will use dmtimer as a kernel clocksource and lead to kernel
      crash during boot  -
      
      [    0.000000] OMAP clocksource: GPTIMER2 at 26000000 Hz
      [    0.000000] sched_clock: 32 bits at 26MHz, resolution 38ns, wraps every
      165191ms
      [    0.000000] Unable to handle kernel paging request at virtual address
      00030ef1
      [    0.000000] pgd = c0004000
      [    0.000000] [00030ef1] *pgd=00000000
      [    0.000000] Internal error: Oops: 5 [#1] SMP
      [    0.000000] Modules linked in:
      [    0.000000] CPU: 0    Not tainted  (3.3.0-rc1-11574-g0c76665-dirty #3)
      [    0.000000] PC is at dmtimer_read_sched_clock+0x18/0x4c
      [    0.000000] LR is at update_sched_clock+0x10/0x84
      [    0.000000] pc : [<c00243b8>]    lr : [<c0018684>]    psr: 200001d3
      [    0.000000] sp : c0641f38  ip : c0641e18  fp : 0000000a
      [    0.000000] r10: 151c3303  r9 : 00000026  r8 : 76276259
      [    0.000000] r7 : 00028547  r6 : c065ac80  r5 : 431bde82  r4 : c0655968
      [    0.000000] r3 : 00030ef1  r2 : fb032000  r1 : 00000028  r0 : 00000001
      Signed-off-by: NVaibhav Hiremath <hvaibhav@ti.com>
      [tony@atomide.com: updated comments]
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      dbc3982a
  3. 26 1月, 2012 12 次提交
  4. 23 1月, 2012 1 次提交
    • W
      ARM: 7291/1: cache: assume 64-byte L1 cachelines for ARMv7 CPUs · a092f2b1
      Will Deacon 提交于
      To ensure correct alignment of cacheline-aligned data, the maximum
      cacheline size needs to be known at compile time.
      
      Since Cortex-A8 and Cortex-A15 have 64-byte cachelines (and it is likely
      that there will be future ARMv7 implementations with the same line size)
      then it makes sense to assume that CPU_V7 implies a 64-byte L1 cacheline
      size. For CPUs with smaller caches, this will result in some harmless
      padding but will help with single zImage work and avoid hitting subtle
      bugs with misaligned data structures.
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      a092f2b1
  5. 21 1月, 2012 2 次提交
  6. 16 1月, 2012 1 次提交
  7. 13 1月, 2012 1 次提交
    • R
      ARM: Add arm_memblock_steal() to allocate memory away from the kernel · 716a3dc2
      Russell King 提交于
      Several platforms are now using the memblock_alloc+memblock_free+
      memblock_remove trick to obtain memory which won't be mapped in the
      kernel's page tables.  Most platforms do this (correctly) in the
      ->reserve callback.  However, OMAP has started to call these functions
      outside of this callback, and this is extremely unsafe - memory will
      not be unmapped, and could well be given out after memblock is no
      longer responsible for its management.
      
      So, provide arm_memblock_steal() to perform this function, and ensure
      that it panic()s if it is used inappropriately.  Convert everyone
      over, including OMAP.
      
      As a result, OMAP with OMAP4_ERRATA_I688 enabled will panic on boot
      with this change.  Mark this option as BROKEN and make it depend on
      BROKEN.  OMAP needs to be fixed, or 137d105d (ARM: OMAP4: Fix
      errata i688 with MPU interconnect barriers.) reverted until such
      time it can be fixed correctly.
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      716a3dc2
  8. 06 1月, 2012 1 次提交
  9. 05 1月, 2012 3 次提交
  10. 19 12月, 2011 4 次提交
  11. 17 12月, 2011 6 次提交
    • P
      OMAP4: mcbsp: Enable FIFO usage · da76250e
      Peter Ujfalusi 提交于
      All McBSP instances on OMAP4 has 128 word long FIFO
      Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
      Acked-by: NTony Lindgren <tony@atomide.com>
      Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
      da76250e
    • S
      ARM: OMAP4: clock: Add CPU local timer clock node · 30c95692
      Santosh Shilimkar 提交于
      Local timer clock is sourced from the CPU clock and hence changes
      along with CPU clock. These per CPU local timers are used as
      clock-events, so they need to be reconfigured on CPU frequency
      change as part of CPUfreq governor.
      
      Newly introduced clockevents_reconfigure() needs to know the
      twd clock-rate. Provide a clock-node to make clk_get_rate() work
      for TWD.
      Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
      Cc: Paul Walmsley <paul@pwsan.com>
      Cc: Kevin Hilman <khilman@ti.com>
      [paul@pwsan.com: renamed clock node to 'mpu_periphclk' to indicate that this
       is the Cortex-A9 MPCore subsystem clock PERIPHCLK (DDI 0407G); moved
       clock and clkdev entries to match the autogenerated script output]
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      30c95692
    • B
      ARM: OMAP4: hwmod: Don't wait for the idle status if modulemode is not supported · bfc141e3
      Benoit Cousson 提交于
      If the module does not have any modulemode, the _disable_module function
      will do nothing. There is then no point waiting for a idle status change.
      
      It will remove the following warnings.
      
      [    0.331848] omap_hwmod: dmm: _wait_target_disable failed
      [    0.339935] omap_hwmod: emif_fw: _wait_target_disable failed
      [    0.348358] omap_hwmod: l3_main_1: _wait_target_disable failed
      [    0.356964] omap_hwmod: l3_main_2: _wait_target_disable failed
      [    0.365600] omap_hwmod: l4_abe: _wait_target_disable failed
      [    0.373931] omap_hwmod: l4_cfg: _wait_target_disable failed
      [    0.382263] omap_hwmod: l4_per: _wait_target_disable failed
      [    0.391113] omap_hwmod: l4_wkup: _wait_target_disable failed
      [    0.399536] omap_hwmod: dma_system: _wait_target_disable failed
      [    0.408325] omap_hwmod: dss_core: _wait_target_disable failed
      [    0.416839] omap_hwmod: dss_dispc: _wait_target_disable failed
      [    0.425445] omap_hwmod: dss_dsi1: _wait_target_disable failed
      [    0.433990] omap_hwmod: dss_dsi2: _wait_target_disable failed
      [    0.442504] omap_hwmod: dss_hdmi: _wait_target_disable failed
      [    0.451019] omap_hwmod: dss_rfbi: _wait_target_disable failed
      [    0.459564] omap_hwmod: dss_venc: _wait_target_disable failed
      [    0.489471] omap_hwmod: mailbox: _wait_target_disable failed
      [    0.505920] omap_hwmod: spinlock: _wait_target_disable failed
      
      Note: For such module, the state is managed automatically by HW according
      to clock domain transition. It is then not possible to wait for idle even
      later in the _idle function since the status will change at clock domain
      boundary.
      Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
      Cc: Paul Walmsley <paul@pwsan.com>
      Cc: Rajendra Nayak <rnayak@ti.com>
      [paul@pwsan.com: renamed fns to indicate that they are OMAP4-only; moved
       _wait_target_disable() into _disable_module(), removing duplicate code]
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      bfc141e3
    • P
      ARM: OMAP: AM3517/3505: fix crash on boot due to incorrect voltagedomain data · ddf536d0
      Paul Walmsley 提交于
      AM3517/3505 chips don't have voltage controller and voltage processor
      IP blocks.  Trying to use OMAP34xx/36xx voltage domain data on these
      chips causes a crash during boot:
      
        omap_vc_init_channel: PMIC info requried to configure vc forvdd_core not populated.Hence cannot initialize vc
        Unable to handle kernel NULL pointer dereference at virtual address 00000025
        pgd = c0004000
        [00000025] *pgd=00000000
        Internal error: Oops: 5 [#1] SMP
        Modules linked in:
        CPU: 0    Tainted: G        W     (3.2.0-rc5-00006-g402ecf4 #304)
        PC is at omap_vp_init+0x5c/0x14c
        LR is at omap_vp_init+0x54/0x14c
      
      Fix this by using very minimal voltage domain definitions for AM3517/3505.
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      Cc: Igor Grinberg <grinberg@compulab.co.il>
      Cc: Kevin Hilman <khilman@ti.com>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      ddf536d0
    • R
      ARM: omap: pass minimal SoC/board data for UART from dt · cf3c79de
      Rajendra Nayak 提交于
      Pass minimal data needed for console boot, from dt, for
      OMAP4 panda/sdp and OMAP3 beagle boards, and get rid of the
      static initialization from generic board file.
      Signed-off-by: NRajendra Nayak <rnayak@ti.com>
      Reviewed-by: NRob Herring <rob.herring@calxeda.com>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      cf3c79de
    • R
      ARM: OMAP2+: hwmod: Add a new flag to handle hwmods left enabled at init · aacf0941
      Rajendra Nayak 提交于
      An hwmod with a 'HWMOD_INIT_NO_IDLE' flag set, is left in
      enabled state by the hwmod framework post the initial setup.
      Once a real user of the device (a driver) tries to enable it
      at a later point, the hwmod framework throws a WARN() about
      the device being already in enabled state.
      
      Fix this by introducing a new internal flag '_HWMOD_SKIP_ENABLE' to
      identify such devices/hwmods. When the device/hwmod is requested to be
      enabled (the first time) by its driver/user, nothing except the
      mux-enable is needed. The mux data is board specific and is
      unavailable during initial enable() of the device, done by the
      framework as part of setup().
      
      A good example of a such a device is an UART used as debug console.
      The UART module needs to be kept enabled through the boot, until the
      UART driver takes control of it, for debug prints to appear on
      the console.
      Acked-by: NKevin Hilman <khilman@ti.com>
      Acked-by: NBenoit Cousson <b-cousson@ti.com>
      Signed-off-by: NRajendra Nayak <rnayak@ti.com>
      [paul@pwsan.com: use a flag rather than a state; updated commit message;
       edited some documentation]
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      aacf0941