This version brings along following fixes:

- Copy crc_skip_count when duplicating CRTC state
- Add debug option for idle optimizations on cursor updates
- Disable MPC split for DCN32/321
- Add missing ODM 2:1 policy logic
- Update DCN32 and DCN321 SR latencies
- Add reinstate dram in the FPO logic
- Add dc_ctx to link_enc_create() parameters
- Cache cursor when cursor exceeds 64x64
- Add support for manual DMUB FAMS trigger
- Fix dpstreamclk programming
- Add missing AUDIO_DTO_SEL reg field
- Add OTG/ODM functions
- Use correct clock source constructor for DCN314
- Use correct DTO_SRC_SEL for 128b/132b encoding
- Add pixel rate div calcs and programming
- Remove FPU flags from DCN30 Makefile
- Create patch bounding box function for isolate FPU
- Move mclk calculation function to DML
- Remove FPU operations from dcn201 resources
- Fallback to SW cursor if SubVP + cursor too big
- Drop unnecessary FPU flags on dcn302 files
- Reboot while unplug hdcp enabled dp from mst hub
- Reset pipe count when iterating for DET override
- Calculate MALL cache lines based on Mblks required
- Fix two MPO videos in single display ODM combine mode
- Guard against zero memory channels
- Updates SubVP + SubVP DRR cases updates
- Fix OPTC function pointers for DCN314
- Add enable/disable FIFO callbacks to stream setup
- Avoid MPC infinite loop
Acked-by: NAlex Hung <alex.hung@amd.com>
Signed-off-by: NAnthony Koo <anthony.koo@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This version brings along following fixes:

- Isolate FPU operation for DCN32/321 under the DML folder
- Create a specific file for CRTC and plane based on amdgpu_dm
- Fix DSC issues
- Update DML logic
Acked-by: NAlan Liu <HaoPing.Liu@amd.com>
Signed-off-by: NAric Cyr <aric.cyr@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Remove an unused variable "remove_disconnect_edp" which was a workaround
bit.
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Acked-by: NAlan Liu <HaoPing.Liu@amd.com>
Signed-off-by: NJun Lei <Jun.Lei@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This version brings along following fixes:

- Fixes for MST, MPO, PSRSU, DP 2.0, Freesync and others
- Add register offsets of NBI and DCN.
- Improvement of ALPM
- Removing assert statement for Linux DM
- Re-implementing ARGB16161616 pixel format
Acked-by: NSolomon Chiu <solomon.chiu@amd.com>
Signed-off-by: NAric Cyr <aric.cyr@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why&How]
Add a field to store the NBIO IP offset for use with runtime offset
calculation
Reviewed-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: NSolomon Chiu <solomon.chiu@amd.com>
Signed-off-by: NAurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why&How]
Add a field to store the DCN IP offset for use with runtime offset
calculation

This offset is indexed using reg*_BASE_IDX for the corresponding
group of registers. For example, address of DIG_BE_CNTL instance 0 is
calculated like: dcn_reg_offsets[regDIG0_DIG_BE_CNTL_BASE_IDX] +
regDIG0_DIG_BE_CNTL.

{dcn,nbio}_reg_offsets are used only for the ASICs for which runtime
initializaion of offsets are enabled through the modified SR* macros
that contain an additional REG_STRUCT element in the macro definition.

DCN3.5+ will fail dc_create() if {dcn,nbio}_reg_offsets are null. They
are applicable starting with DCN32/321 and are not used for ASICs
upstreamed before them. ASICs before DCN32/321 will not contain any
computation that involves {dcn,nbio}_reg_offsets. For them, the
address/offset computation is done during compile time.

This is evident from the BASE_INNER definition for compile time vs run
time initialization:

Compile time init: #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
Run time init:     #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]

BASE_INNER macro is local to each dcnxx_resource.c and hence different
ASICs can have either runtime or compile time initialization of offsets.

The computation of offset is done for registers all at once during
driver load and hence it does not introduce any performance overhead
during normal operation.
Reviewed-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: NSolomon Chiu <solomon.chiu@amd.com>
Signed-off-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Acked-by: NSolomon Chiu <solomon.chiu@amd.com>
Signed-off-by: NAric Cyr <aric.cyr@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Description]
Exit SubVP if MPO is in use since SubVP + MPO together is not supported.
- Don't add SubVP at validation time if we see MPO is in use

Issues fixed in the SubVP / MPO transition:
1. Enable phantom pipes in post unlock function to prevent underflow
when an active pipe is being transitioned to be a phantom pipe (VTG
updates take place right away). Also must wait for VUPDATE of the main
pipe to complete first

2. Don't wait for MPCC idle when transitioning a phantom pipe to an
actual pipe. MPCC_STATUS is never asserted due to OTG being off for
phantom pipes

3. When transitioning an active pipe to phantom, program DET right away
(same as disabling the pipe) or the DET update will only take when
the phantom pipe is enabled which can cause DET allocation errors.

4. For K1/K2 programming of phantom pipes, use same settings as the
main pipe. Also don't program K1 / K2 = 0xF ever since the field is only
1 / 2 bits wide.
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NSolomon Chiu <solomon.chiu@amd.com>
Signed-off-by: NAlvin Lee <Alvin.Lee2@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This DC patchset brings improvements in multiple areas. In summary, we
highlight:

- Program ACP-related registers
- Fixes for DMUB, DPIA, PSR, and others
- Improvements in the pipe split
- Add SubVP code
- Add basic setup for FAMS support
- Improve BB capabilities
Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: NAric Cyr <aric.cyr@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

hdmi_frl_pcon_support has been the source of confusion. So, rename it to
dp_hdmi21_pcon_support.
Signed-off-by: NHamza Mahfooz <hamza.mahfooz@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Some panels may require more MST delay on discovery

[How]
Add panel patch and debug mst delay flag
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: NDuncan Ma <duncan.ma@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Some TBT3 docks have DPOAs which report USB4 capability and are expected
to support USB4 DPOA features such as FEC/DSC.

[How]
By default, do not override FEC/DSC capabilities reported by TBT3 docks.
Reviewed-by: NMeenakshikumar Somasundaram <Meenakshikumar.Somasundaram@amd.com>
Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: NJimmy Kizito <Jimmy.Kizito@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
DC debug option to configure dpia hpd processing delay is not required.

[How]
Remove dc debug option for dpia hpd delay and also added log for
querying dpia hpd state.
Reviewed-by: NMustapha Ghaddar <Mustapha.Ghaddar@amd.com>
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: NMeenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

We want to enable Firmware Assisted Memory (FAMS) Switching, but first,
we need to add the required code infrastructure in DC before allowing it
in amdgpu_dm.
Signed-off-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Newer DCN should use optc3

[How]
Declare optc3 vmin/vmax function in header.
Signed-off-by: NAlvin Lee <Alvin.Lee2@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Most of the time, a single display uses the ODM combine. When using
multi-display, we use ODM combine only if it is necessary. These cases
are not flexible enough for us, and we can improve them to take
advantage of our hardware. We want to have more control over the ODM
policy.

[How]
This commit add a new debug flag named
enable_single_display_2to1_odm_policy to control the ODM policy and
another flag named enable_dp_dig_pixel_rate_div_policy to fine control
the ODM combine. This is possible by adding a new "pipe.dest" parameter
that can be set to ODM 2:1 combined if we use a single display. For
dynamic ODM combine, when using DP-DIG, DCN applies K2=2 settings for
ODM combine. Note that this feature affects the following registers:

- timing.pix_clk_100khz -> DP_VID_M, DP_VID_N
- requested_pix_clk_100hz -> DP_DTOn_PHASE
- OTGn_PIXEL_RATE_DIVK2
- DP_PIXEL_PER_CYCLE_PROCESSING_MODE
- DIG_FIFO_OUTPUT_PIXEL_MODE
- DP_VID_N_MUL
Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: NSamson Tam <Samson.Tam@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This commit enables the SubVP feature. To achieve that, we need to:

- Don't force p-state disallow on SubVP (can't block dummy p-state)
- Send calculated watermark to DMCUB for SubVP
- Adjust CAB mode message to PMFW
- Add a proper locking sequence for SubVP
- Various fixes to SubVP static analysis and determining SubVP config
- Currently SubVP not supported with pipe split so merge all pipes
  before setting up SubVp
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: NAlan Liu <HaoPing.Liu@amd.com>
Signed-off-by: NAlvin Lee <Alvin.Lee2@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This DC patchset brings improvements in multiple areas. In summary, we
highlight:

- Remove unnecessary code;
- Small fixes (compilation warnings, typos, etc);
- Improvements in the DPMS code;
- Fix eDP issues
- Improvements in the MST code
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: NAric Cyr <aric.cyr@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why & How]
Old vendor specific w/a are no longer needed and unused. Clean up
codebase by removing them.
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: NWenjing Liu <Wenjing.Liu@amd.com>
Acked-by: NAlan Liu <HaoPing.Liu@amd.com>
Signed-off-by: NGeorge Shen <george.shen@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Several issues were discovered that caused link
training to fail when an LTTPR device is
connected downstream for the fixed VS sequence.

[How]
The following were added:
- workaround to configure AUX timeout
for fixed VS sequence
- additional delay before disabling
fixed VS intercept
- detection of fixed VS deadlock state and
performing DPCD sequence to recover
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: NMeenakshikumar Somasundaram <Meenakshikumar.Somasundaram@amd.com>
Acked-by: NAlan Liu <HaoPing.Liu@amd.com>
Signed-off-by: NGeorge Shen <George.Shen@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
Only on VG, if external display is disconnected during S3 suspend, the
internal panel doesn't light up on resume because we set the power state
using an unsupported DPCD register SET_POWER.  To check the register is
supported, we need to check SET_POWER_CAPABLE first which is
eDP-specific DPCD register field.

[how]
Check the SET_POWER_CAPABLE register field and decide the control of the
eDP power state based on the read register value.
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: NAgustin Gutierrez <Agustin.Gutierrez@amd.com>
Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: NSung Joon Kim <sungkim@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
All displays need to be blanked during the uclk OC interface so that we can
guarantee pstate switching support. If the display config doesn't support
pstate switching, only using core_link_disable_stream will not enable it
as the front-end is untouched. We need to go through the full plane removal
sequence to properly program the pipe to allow pstate switching.

[How]
 - guard clk_mgr functions with non-NULL checks
Acked-by: NAlan Liu <HaoPing.Liu@amd.com>
Signed-off-by: NJoshua Aberback <joshua.aberback@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This version brings along the following:
- DP fixes
- Exiting idle optimizations on mouse updates
Acked-by: NHamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: NAric Cyr <aric.cyr@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Description]
- Have option to exit idle opt on cursor updates
for debug and optimizations purposes
Reviewed-by: NSamson Tam <Samson.Tam@amd.com>
Acked-by: NHamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: NAlvin Lee <Alvin.Lee2@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This version brings along the following:
- DPP DTO fix
- Transient encoder fix
- Restrict the reading of LTTPR capabilities in LTTPR mode
- Increase maximum stages for BB
- Distinguish HDMI DTO from DP DTO
Acked-by: NHamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: NAric Cyr <aric.cyr@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
Some parts are consuming dangerously close to maximum number of states
supported when updating the BB (i.e. 8).

[how]
Change maximum stages from 9 to 20.
Reviewed-by: NAlvin Lee <Alvin.Lee2@amd.com>
Acked-by: NHamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: NJun Lei <jun.lei@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This version brings along the following:
- Optimized blank calculations
- More robust DP MST hotplug support
- eDP bug fix relating to ODM
- Revert a patch that caused a regression with DP
- min comp buffer size fix
- Make DP easier to debug
- Calculate the maximum OLED brightness correctly
- 3 plane MPO.
Acked-by: NHamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: NAric Cyr <aric.cyr@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
For panels with pixel clock > 1200MHz that require ODM
in pre-OS, when driver is disabled in OS, odm is enabled.
Upon driver enablement, corruption is seen if
odm was originally enabled. DP_PIXEL_COMBINE and
pixelclk must be programmed prior to programming the
optc-odm registers. However, eDP displays aren't blanked
prior to initializing odm in this case.

[How]
Upon driver enablement, check whether odm is enabled,
if so, blank eDP prior to programming optc-odm
registers.
Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: NHamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: NDuncan Ma <duncan.ma@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[WHY & HOW]
Implements DTB ref clock switching with reg key default to OFF.
Refactors dccg DTBCLK logic to not store redundant state information
dccg. Also removes duplicated functions that should be inherited from
other dcn versions.
Signed-off-by: NAlvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why&How]
This patch adds necessary changes needed in DC files outside DCN32/321
specific tree

v2: squash in updates (Alex)
Signed-off-by: NAurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Add support for managing DCN3.2.x clocks.

v2: squash in smu interface updates (Alex)
v3: Drop unused SMU header (Alex)
Signed-off-by: NAurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: NJerry Zuo <jerry.zuo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

why:
lut pipeline will be hooked up differently in some asics
need to add new interfaces

how:
add them
Reviewed-by: NKrunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: NJasdeep Dhillon <jdhillon@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NMartin <martin.leung@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This version brings along the following fixes:

* Changes to DP LT fallback behavior to more closely match the DP standard
* Added new interfaces for lut pipeline
* Restore ref_dtblck value when clk struct is cleared in init_clocks
* Fixes DMUB outbox trace in S4
* Fixes lingering DIO FIFO errors when DIO no longer enabled
* Reads Golden Settings Table from VBIOS
Acked-by: NJasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: NAric Cyr <aric.cyr@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

why and how:
Revert this change. It was causing a black screen with certain blocks
Reviewed-by: NGeorge Shen <George.Shen@amd.com>
Acked-by: NJasdeep Dhillon <jdhillon@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NLeung, Martin <Martin.Leung@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

According to the KMS man page, there is a
"Coverage" alpha blend mode that assumes the
pixel color values have NOT been pre-multiplied
and will be done when the actual blending to
the background color values happens.

Previously, this mode hasn't been enabled
in our driver and it was assumed that all
normal overlay planes are pre-multiplied
by default.

When a 3rd party app is used to input a image
in a specific format, e.g. PNG, as a source
of a overlay plane to blend with the background
primary plane, the pixel color values are not
pre-multiplied. So by adding "Coverage" blend
mode, our driver will support those cases.

Issue fixed: Overlay plane alpha channel blending is incorrect
Issue tracker: https://gitlab.freedesktop.org/drm/amd/-/issues/1769

Reference:
https://dri.freedesktop.org/docs/drm/gpu/drm-kms.html#plane-composition-properties

Adding Coverage support also enables IGT
kms_plane_alpha_blend Coverage subtests:
1. coverage-7efc
2. coverage-vs-premult-vs-constant

Changes
1. Add DRM_MODE_BLEND_COVERAGE blend mode capability
2. Add "pre_multiplied_alpha" flag for Coverage case
3. Read the correct flag and set the DCN MPCC
pre_multiplied register bit (only on overlay plane)

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1769Signed-off-by: NSung Joon Kim <Sungjoon.Kim@amd.com>
Reviewed-by: NMelissa Wen <mwen@igalia.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This version brings along the following:
- Improvements in link training fallback
- Adding individual edp hotplug support
- Fixes in DPIA HPD status, display clock change hang, etc.
- FPU isolation work for DCN30
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NAric Cyr <aric.cyr@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Second eDP can send display off notification through HPD
but DC isn't hooked up to handle. Some primary eDP panels
will toggle on/off incorrectly if it's enabled generically.

[How]
Extend the debug option to allow individually enabling hotplug
either the first eDP or the second eDP in a dual eDP system.
Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NDerek Lai <Derek.Lai@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This version brings along following fixes:
- Refactor LTTPR code
- Fix PSR after hibernate
- Fix DC build errors
- Fix IRQ unregister error when unloading amdgpu
- Improve DP link training
- Fix stutter
- Remove redundant CONFIG_DRM_AMD_DC_DCN guards
- Fix 2nd connected USB-C display not lighting up
Acked-by: NStylon Wang <stylon.wang@amd.com>
Signed-off-by: NAric Cyr <aric.cyr@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why & How]
CONFIG_DRM_AMD_DC_DCN is used by pass the compilation failures, but DC
code should be OS-agnostic.

This patch fixes it by removing unnecessasry CONFIG_DRM_AMD_DC_DCN
in dc and dc/core directories.
Reviewed-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: NStylon Wang <stylon.wang@amd.com>
Signed-off-by: NAlex Hung <alex.hung@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why & How]
Move definition of dc_flip_addrs struct from dc.h to dc_hw_types.h to
prevent build errors
Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NStylon Wang <stylon.wang@amd.com>
Signed-off-by: NJosip Pavic <Josip.Pavic@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>