- 31 8月, 2022 17 次提交
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由 Oleksij Rempel 提交于
Use chip_id as other places of this code do it Signed-off-by: NOleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: NVladimir Oltean <olteanv@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Oleksij Rempel 提交于
This variable is not used. So, remove it. Signed-off-by: NOleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: NVladimir Oltean <olteanv@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Oleksij Rempel 提交于
This variable is not used on ksz9477 side. Remove it. Signed-off-by: NOleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: NVladimir Oltean <olteanv@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Oleksij Rempel 提交于
This variable is unused. So, drop it. Signed-off-by: NOleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: NVladimir Oltean <olteanv@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Oleksij Rempel 提交于
With code refactoring was introduced new variable internal_phy. Let's use it. Signed-off-by: NOleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: NVladimir Oltean <olteanv@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Oleksij Rempel 提交于
Add register validation for KSZ9477 Signed-off-by: NOleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: NVladimir Oltean <olteanv@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Oleksij Rempel 提交于
The reason why PHYlib may access MII_CTRL1000 on the chip without GBit support is only if chip provides wrong information about extended caps register. This issue is now handled by ksz9477_r_phy_quirks() With proper regmap_ranges provided for all chips we will be able to catch this kind of bugs any way. So, remove this sanity check. Signed-off-by: NOleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: NVladimir Oltean <olteanv@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Oleksij Rempel 提交于
Add register validation for KSZ8563. Signed-off-by: NOleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: NVladimir Oltean <olteanv@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Oleksij Rempel 提交于
This is complex driver with support for different chips with different layouts. To detect at least some bugs earlier, we should validate register accesses by using regmap_access_table support. Signed-off-by: NOleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: NVladimir Oltean <olteanv@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Oleksij Rempel 提交于
This issue was detected after adding regmap register access validation. KSZ9893 compatible chips do not have "Output Clock Control Register 0x0103". So, avoid writing to it. Signed-off-by: NOleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: NVladimir Oltean <olteanv@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Oleksij Rempel 提交于
Now ksz_pread/ksz_pwrite can return error value. So, make use of it. Signed-off-by: NOleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: NVladimir Oltean <olteanv@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Oleksij Rempel 提交于
Now ksz_pread/ksz_pwrite can return error value. So, make use of it. Signed-off-by: NOleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: NVladimir Oltean <olteanv@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Oleksij Rempel 提交于
ksz_read*/ksz_write* are able to return errors, so forward it. Signed-off-by: NOleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: NVladimir Oltean <olteanv@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Oleksij Rempel 提交于
PHY access may end with errors on different levels. So, allow to forward return values where possible. Signed-off-by: NOleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: NVladimir Oltean <olteanv@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Oleksij Rempel 提交于
This issue was detected after adding support of regmap_ranges for KSZ8563R chip. This chip is reporting extended registers support without having actual extended registers. This made PHYlib request not existing registers. Signed-off-by: NOleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: NVladimir Oltean <olteanv@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Oleksij Rempel 提交于
KSZ8563 has two 100Mbit PHYs and CPU port with RGMII support. Since 1000Mbit configuration for the RGMII capable MAC is present, we should use per port validation. As main part of migration to per-port validation we need to rework ksz9477_switch_init() function. Which is using undocumented REG_GLOBAL_OPTIONS register to detect per-chip Gbit support. So, it is related to some sort of risk for regressions. To reduce this risk I compared the code with publicly available documentations. This function will executed on following currently supported chips: struct ksz_chip_data OF compatible KSZ9477 KSZ9477 KSZ9897 KSZ9897 KSZ9893 KSZ9893, KSZ9563 KSZ8563 KSZ8563 KSZ9567 KSZ9567 Only KSZ9893, KSZ9563, KSZ8563 document existence of 0xf == REG_GLOBAL_OPTIONS register with bit field description "SKU ID": KSZ9893 0x0C KSZ9563 0x1C KSZ8563 0x3C The existence of hidden flags is not documented. KSZ9477, KSZ9897, KSZ9567 do not document this register at all. Only KSZ8563 is documented as non Gbit chip: 100Mbit PHYs and RGMII CPU port. So, this change should not introduce a regression for configurations with properly used OF compatibles. Signed-off-by: NOleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: NVladimir Oltean <olteanv@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Oleksij Rempel 提交于
Add separate entry for the KSZ8563 chip. According to the documentation it can support Gbit only on RGMII port. So, we will need to be able to describe in the followup patch. Signed-off-by: NOleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: NVladimir Oltean <olteanv@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 24 8月, 2022 1 次提交
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由 Vladimir Oltean 提交于
Address learning should initially be turned off by the driver for port operation in standalone mode, then the DSA core handles changes to it via ds->ops->port_bridge_flags(). Leaving address learning enabled while ports are standalone breaks any kind of communication which involves port B receiving what port A has sent. Notably it breaks the ksz9477 driver used with a (non offloaded, ports act as if standalone) bonding interface in active-backup mode, when the ports are connected together through external switches, for redundancy purposes. This fixes a major design flaw in the ksz9477 and ksz8795 drivers, which unconditionally leave address learning enabled even while ports operate as standalone. Fixes: b987e98e ("dsa: add DSA switch driver for Microchip KSZ9477") Link: https://lore.kernel.org/netdev/CAFZh4h-JVWt80CrQWkFji7tZJahMfOToUJQgKS5s0_=9zzpvYQ@mail.gmail.com/Reported-by: NBrian Hutchinson <b.hutchman@gmail.com> Signed-off-by: NVladimir Oltean <vladimir.oltean@nxp.com> Link: https://lore.kernel.org/r/20220818164809.3198039-1-vladimir.oltean@nxp.comSigned-off-by: NJakub Kicinski <kuba@kernel.org>
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- 23 8月, 2022 1 次提交
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由 Vladimir Oltean 提交于
DSA has multiple ways of specifying a MAC connection to an internal PHY. One requires a DT description like this: port@0 { reg = <0>; phy-handle = <&internal_phy>; phy-mode = "internal"; }; (which is IMO the recommended approach, as it is the clearest description) but it is also possible to leave the specification as just: port@0 { reg = <0>; } and if the driver implements ds->ops->phy_read and ds->ops->phy_write, the DSA framework "knows" it should create a ds->slave_mii_bus, and it should connect to a non-OF-based internal PHY on this MDIO bus, at an MDIO address equal to the port address. There is also an intermediary way of describing things: port@0 { reg = <0>; phy-handle = <&internal_phy>; }; In case 2, DSA calls phylink_connect_phy() and in case 3, it calls phylink_of_phy_connect(). In both cases, phylink_create() has been called with a phy_interface_t of PHY_INTERFACE_MODE_NA, and in both cases, PHY_INTERFACE_MODE_NA is translated into phy->interface. It is important to note that phy_device_create() initializes dev->interface = PHY_INTERFACE_MODE_GMII, and so, when we use phylink_create(PHY_INTERFACE_MODE_NA), no one will override this, and we will end up with a PHY_INTERFACE_MODE_GMII interface inherited from the PHY. All this means that in order to maintain compatibility with device tree blobs where the phy-mode property is missing, we need to allow the "gmii" phy-mode and treat it as "internal". Fixes: 2c709e0b ("net: dsa: microchip: ksz8795: add phylink support") Link: https://bugzilla.kernel.org/show_bug.cgi?id=216320Reported-by: NCraig McQueen <craig@mcqueen.id.au> Signed-off-by: NVladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: NAlvin Šipraga <alsi@bang-olufsen.dk> Tested-by: NRasmus Villemoes <rasmus.villemoes@prevas.dk> Link: https://lore.kernel.org/r/20220818143250.2797111-1-vladimir.oltean@nxp.comSigned-off-by: NJakub Kicinski <kuba@kernel.org>
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- 18 8月, 2022 1 次提交
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由 Arun Ramadoss 提交于
In the ksz9477_fdb_dump function it reads the ALU control register and exit from the timeout loop if there is valid entry or search is complete. After exiting the loop, it reads the alu entry and report to the user space irrespective of entry is valid. It works till the valid entry. If the loop exited when search is complete, it reads the alu table. The table returns all ones and it is reported to user space. So bridge fdb show gives ff:ff:ff:ff:ff:ff as last entry for every port. To fix it, after exiting the loop the entry is reported only if it is valid one. Fixes: b987e98e ("dsa: add DSA switch driver for Microchip KSZ9477") Signed-off-by: NArun Ramadoss <arun.ramadoss@microchip.com> Reviewed-by: NVladimir Oltean <olteanv@gmail.com> Link: https://lore.kernel.org/r/20220816105516.18350-1-arun.ramadoss@microchip.comSigned-off-by: NJakub Kicinski <kuba@kernel.org>
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- 27 7月, 2022 9 次提交
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由 Arun Ramadoss 提交于
This patch add support for phylink mac config for ksz series of switches. All the files ksz8795, ksz9477 and lan937x uses the ksz common xmii function. Instead of calling from the individual files, it is moved to the ksz common phylink mac config function. Signed-off-by: NArun Ramadoss <arun.ramadoss@microchip.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Arun Ramadoss 提交于
This patch updates the ksz8795 cpu configuration to use the ksz common xmii set functions. Signed-off-by: NArun Ramadoss <arun.ramadoss@microchip.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Arun Ramadoss 提交于
In ksz9477.c file, configuring the xmii register is performed based on the flag NEW_XMII. The flag is reset for ksz9893 switch and set for other switch. This patch uses the ksz common xmii set and get function. The bit values are configured based on the chip id. Signed-off-by: NArun Ramadoss <arun.ramadoss@microchip.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Arun Ramadoss 提交于
This patch read the rgmii tx and rx delay from device tree and stored it in the ksz_port. It applies the rgmii delay to the xmii tune adjust register based on the interface selected in phylink mac config. There are two rgmii port in LAN937x and value to be loaded in the register vary depends on the port selected. Signed-off-by: NArun Ramadoss <arun.ramadoss@microchip.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Arun Ramadoss 提交于
This patch add the common ksz_set_xmii function for ksz series switch and update the lan937x code phylink mac config. The register address for the ksz8795 is Port 5 Interface control 6 and for all other switch is xMII Control 1. The bit value for selecting the interface is same for KSZ8795 and KSZ9893 are same. The bit values for KSZ9477 and lan973x are same. So, this patch add the bit value for each switches in ksz_chip_data and configure the registers based on the chip id. Signed-off-by: NArun Ramadoss <arun.ramadoss@microchip.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Arun Ramadoss 提交于
This patch add the support for common phylink mac link up for the ksz series switch. The register address, bit position and values are configured based on the chip id to the dev->info structure. Signed-off-by: NArun Ramadoss <arun.ramadoss@microchip.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Arun Ramadoss 提交于
This patch add common function for configuring the Full/Half duplex and transmit/receive flow control. KSZ8795 uses the Global control register 4 for configuring the duplex and flow control, whereas all other KSZ9477 based switch uses the xMII Control 0 register. Signed-off-by: NArun Ramadoss <arun.ramadoss@microchip.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Arun Ramadoss 提交于
This patch adds the function for configuring the 100/10Mbps speed selection for the ksz switches. KSZ8795 switch uses Global control 4 register 0x06 bit 4 for choosing 100/10Mpbs. Other switches uses xMII control 1 0xN300 for it. For KSZ8795, if the bit is set then 10Mbps is chosen and if bit is clear then 100Mbps chosen. For all other switches it is other way around, if the bit is set then 100Mbps is chosen. So, this patch add the generic function for ksz switch to select the 100/10Mbps speed selection. While configuring, first it disables the gigabit functionality and then configure the respective speed. Signed-off-by: NArun Ramadoss <arun.ramadoss@microchip.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Arun Ramadoss 提交于
This patch add helper function for setting and getting the gigabit enable for the ksz series switch. KSZ8795 switch has different register address compared to all other ksz switches. KSZ8795 series uses the Port 5 Interface control 6 Bit 6 for configuring the 1Gbps or 100/10Mbps speed selection. All other switches uses the xMII control 1 0xN301 register Bit6 for gigabit. Further, for KSZ8795 & KSZ9893 switches if bit 1 then 1Gbps is chosen and if bit 0 then 100/10Mbps is chosen. It is other way around for other switches bit 0 is for 1Gbps. So, this patch implements the common function for configuring the gigabit set and get capability. Signed-off-by: NArun Ramadoss <arun.ramadoss@microchip.com> Reviewed-by: NVladimir Oltean <olteanv@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 19 7月, 2022 1 次提交
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由 Arun Ramadoss 提交于
During the refactoring for the ksz8_dev_ops from ksz8795.c to ksz_common.c, the ksz8_r_mib_cnt has been missed. So this patch adds the missing one. Fixes: 6ec23aaa ("net: dsa: microchip: move ksz_dev_ops to ksz_common.c") Signed-off-by: NArun Ramadoss <arun.ramadoss@microchip.com> Reviewed-by: NVladimir Oltean <olteanv@gmail.com> Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20220718061803.4939-1-arun.ramadoss@microchip.comSigned-off-by: NPaolo Abeni <pabeni@redhat.com>
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- 18 7月, 2022 1 次提交
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由 Arun Ramadoss 提交于
This patch removes the of_match_ptr() pointer when dereferencing the ksz_dt_ids which produce the unused variable warning. Reported-by: Nkernel test robot <lkp@intel.com> Suggested-by: NArnd Bergmann <arnd@kernel.org> Signed-off-by: NArun Ramadoss <arun.ramadoss@microchip.com> Reviewed-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 16 7月, 2022 1 次提交
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由 Liang He 提交于
In ksz_switch_register(), we should call of_node_put() for the reference returned by of_get_child_by_name() which has increased the refcount. Fixes: 912aae27 ("net: dsa: microchip: really look for phy-mode in port nodes") Signed-off-by: NLiang He <windhl@126.com> Reviewed-by: NVladimir Oltean <olteanv@gmail.com> Link: https://lore.kernel.org/r/20220714153138.375919-1-windhl@126.comSigned-off-by: NJakub Kicinski <kuba@kernel.org>
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- 02 7月, 2022 8 次提交
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由 Arun Ramadoss 提交于
This patch add the LAN937x part support in the existing ksz_spi_probe. Signed-off-by: NArun Ramadoss <arun.ramadoss@microchip.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Arun Ramadoss 提交于
This patch add support for phylink_mac_config dsa hook. It configures the mac for MII/RMII modes. The RGMII mode will be added in the future patches. Signed-off-by: NArun Ramadoss <arun.ramadoss@microchip.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Arun Ramadoss 提交于
This patch add support for phylink_mac_link_up. It configures the mac for the speed, flow control and duplex mode. Signed-off-by: NArun Ramadoss <arun.ramadoss@microchip.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Arun Ramadoss 提交于
The internal phy of the LAN937x are capable of 100Mbps Full duplex. The xMII port of switch is capable of 10Mbps Full & Half Duplex, 100Mbps Full & Half Duplex and 1000Mbps Half duplex. xMII port also supports Tx and Rx Flow control. Signed-off-by: NArun Ramadoss <arun.ramadoss@microchip.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Arun Ramadoss 提交于
This patch add the support for port_max_mtu, port_change_mtu and port_fast_age dsa functionality. Signed-off-by: NArun Ramadoss <arun.ramadoss@microchip.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Arun Ramadoss 提交于
This patch register mdio-bus for the lan937x series switch. mdio read and write uses the vphy for accessing the phy register. Signed-off-by: NArun Ramadoss <arun.ramadoss@microchip.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Arun Ramadoss 提交于
This patch add support for the writing and reading of the phy registers. LAN937x uses the Vphy indirect addressing method for accessing the phys. Signed-off-by: NArun Ramadoss <arun.ramadoss@microchip.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Arun Ramadoss 提交于
This patch update the ksz_get_tag_protocol to return LAN937x specific tag if the chip id matches one of LAN937x series switch Signed-off-by: NArun Ramadoss <arun.ramadoss@microchip.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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