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  1. 08 4月, 2015 4 次提交
  3. 17 2月, 2015 13 次提交
  5. 24 11月, 2014 1 次提交
    • P
      MIPS: Support for hybrid FPRs · 4227a2d4
      由 Paul Burton 提交于 
      Hybrid FPRs is a scheme where scalar FP registers are 64b wide, but
accesses to odd indexed single registers use bits 63:32 of the
preceeding even indexed 64b register. In this mode all FP code
except that built for the plain FP64 ABI can execute correctly. Most
notably a combination of FP64A & FP32 code can execute correctly,
allowing for existing FP32 binaries to be linked with new FP64A binaries
that can make use of 64 bit FP & MSA.

Hybrid FPRs are implemented by setting both the FR & FRE bits, trapping
& emulating single precision FP instructions (via Reserved Instruction
exceptions) whilst allowing others to execute natively. It therefore has
a penalty in terms of execution speed, and should only be used when no
fully native mode can be. As more binaries are recompiled to use either
the FPXX or FP64(A) ABIs, the need for hybrid FPRs should diminish.
However in the short to mid term it allows for a gradual transition
towards that world, rather than a complete ABI break which is not
feasible for some users & not desirable for many.

A task will be executed using the hybrid FPR scheme when its
TIF_HYBRID_FPREGS flag is set & TIF_32BIT_FPREGS is clear. A further
patch will set the flags as necessary, this patch simply adds the
infrastructure necessary for the hybrid FPR mode to work.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Alexander Viro <viro@zeniv.linux.org.uk>
Cc: linux-fsdevel@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/7683/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      4227a2d4
  7. 07 11月, 2014 1 次提交
    • M
      MIPS: Fix build with binutils 2.24.51+ · 842dfc11
      由 Manuel Lauss 提交于 
      Starting with version 2.24.51.20140728 MIPS binutils complain loudly
about mixing soft-float and hard-float object files, leading to this
build failure since GCC is invoked with "-msoft-float" on MIPS:

{standard input}: Warning: .gnu_attribute 4,3 requires `softfloat'
  LD      arch/mips/alchemy/common/built-in.o
mipsel-softfloat-linux-gnu-ld: Warning: arch/mips/alchemy/common/built-in.o
 uses -msoft-float (set by arch/mips/alchemy/common/prom.o),
 arch/mips/alchemy/common/sleeper.o uses -mhard-float

To fix this, we detect if GAS is new enough to support "-msoft-float" command
option, and if it does, we can let GCC pass it to GAS;  but then we also need
to sprinkle the files which make use of floating point registers with the
necessary ".set hardfloat" directives.
Signed-off-by: NManuel Lauss <manuel.lauss@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
Cc: Markos Chandras <Markos.Chandras@imgtec.com>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/8355/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      842dfc11
  9. 21 10月, 2014 1 次提交
  11. 26 9月, 2014 1 次提交
    • P
      MIPS: Fix MFC1 & MFHC1 emulation for 64-bit MIPS systems · c8c0da6b
      由 Paul Burton 提交于 
      Commit bbd426f5 "MIPS: Simplify FP context access" modified the
SIFROMREG & SIFROMHREG macros such that they return unsigned rather
than signed 32b integers. I had believed that to be fine, but
inadvertently missed the MFC1 & MFHC1 cases which write to a struct
pt_regs regs element. On MIPS32 this is fine, but on 64 bit those
saved regs' fields are 64 bit wide. Using unsigned values caused the
32 bit value from the FP register to be zero rather than sign extended
as the architecture specifies, causing incorrect emulation of the
MFC1 & MFHc1 instructions. Fix by reintroducing the casts to signed
integers, and therefore the sign extension.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
Cc: stable@vger.kernel.org # v3.15+
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7848/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      c8c0da6b
  13. 31 7月, 2014 1 次提交
  15. 31 5月, 2014 1 次提交
  17. 30 5月, 2014 1 次提交
  19. 23 5月, 2014 5 次提交
    • R
      MIPS: math-emu: Reduce microMIPS bloat. · 70e4c234
      由 Ralf Baechle 提交于 
      Move microMIPS32_to_MIPS32() to a separate file which only gets built
for mipsMIPS configurations; for other configurations the optimizer
eleminates calls to microMIPS32_to_MIPS32().
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      70e4c234
    • R
      MIPS: math-emu: Switch to using the MIPS rounding modes. · 56a64733
      由 Ralf Baechle 提交于 
      Previously math-emu was using the IEEE-754 constants internally.  These
were differing by having the constants for rounding to +/- infinity
switched, so a conversion was necessary.  This would be entirely
avoidable if the MIPS constants were used throughout, so get rid of
the bloat.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      56a64733
    • R
      MIPS: Sort out mm_isBranchInstr. · 76fbfc31
      由 Ralf Baechle 提交于 
      mm_isBranchInstr() did reside in the math emu code even though it logically
is separate and also is used outside the math emu code.  In addition GCC 4.9.0
leaves the following unnnecessarily bloated function body for a non-microMIPS
configuration:

<mm_isBranchInstr>:
    105c:       afa50004        sw      a1,4(sp)
    1060:       afa60008        sw      a2,8(sp)
    1064:       afa7000c        sw      a3,12(sp)
    1068:       03e00008        jr      ra
    106c:       00001021        move    v0,zero

which stores arguments that are never going to be used on the stack frame.

Move mm_isBranchInstr() from cp1emu.c to branch.c, then split mm_isBranchInstr()
into a __mm_isBranchInstr() core and a mm_isBranchInstr() wrapper inline function
which only invokes __mm_isBranchInstr() on microMIPS configurations.

This shaves off 112 bytes off the kernel and improves code flow a bit.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      76fbfc31
    • R
      MIPS: math-emu: Cleanup coding style. · 3f7cac41
      由 Ralf Baechle 提交于 
       o Only define variables in the outermost block
 o One empty line at most
 o Format comments as per CodingStyle
 o Update FSF address in licensing term comment
 o Spell FPU and MIPS in all capitals.
 o Remove ####-type of lines in comments.
 o Try to make things a bit most consistent between sp_*.c / dp_*.c files.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      3f7cac41
    • R
      MIPS: math-emu: Convert debug printks to pr_debug getting. · 92df0f8b
      由 Ralf Baechle 提交于 
      And another bunch of #ifdefs bite the dust.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      92df0f8b
  21. 21 5月, 2014 6 次提交
  23. 27 3月, 2014 2 次提交
  25. 12 3月, 2014 1 次提交
  27. 14 1月, 2014 2 次提交