Add functions for RAS error inject and query error counter
Signed-off-by: NDennis Li <Dennis.Li@amd.com>
Reviewed-by: NTao Zhou <tao.zhou1@amd.com>
Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NDennis Li <Dennis.Li@amd.com>
Reviewed-by: NTao Zhou <tao.zhou1@amd.com>
Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NDennis Li <Dennis.Li@amd.com>
Reviewed-by: NTao Zhou <tao.zhou1@amd.com>
Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Add EDC registers to support VEGA20 RAS
Signed-off-by: NDennis Li <Dennis.Li@amd.com>
Reviewed-by: NTao Zhou <tao.zhou1@amd.com>
Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

error injection address is not in gpu address space
Signed-off-by: NTao Zhou <tao.zhou1@amd.com>
Reviewed-by: NDennis Li <dennis.li@amd.com>
Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

only ue and ce errors are supported
Signed-off-by: NTao Zhou <tao.zhou1@amd.com>
Reviewed-by: NDennis Li <dennis.li@amd.com>
Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

add err_data parameter in interrupt cb for ras clients
Signed-off-by: NTao Zhou <tao.zhou1@amd.com>
Reviewed-by: NDennis Li <dennis.li@amd.com>
Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

add error data as parameter for ras interrupt cb and process it
Signed-off-by: NTao Zhou <tao.zhou1@amd.com>
Reviewed-by: NDennis Li <dennis.li@amd.com>
Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

query umc ras error address, translate it to gpu 4k page view
and save it.
Signed-off-by: NTao Zhou <tao.zhou1@amd.com>
Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: NDennis Li <dennis.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

add related registers, callback function and channel index table
Signed-off-by: NTao Zhou <tao.zhou1@amd.com>
Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

more than one error address may be recorded in one query
Signed-off-by: NTao Zhou <tao.zhou1@amd.com>
Reviewed-by: NDennis Li <dennis.li@amd.com>
Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

remove the check of ErrorCodeExt

v2: refine the if condition for ue counting
Signed-off-by: NTao Zhou <tao.zhou1@amd.com>
Reviewed-by: NDennis Li <dennis.li@amd.com>
Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

create new amdgpu_umc structure to for more umc
settings in future and switch to the new structure
Signed-off-by: NTao Zhou <tao.zhou1@amd.com>
Signed-off-by: NHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: NDennis Li <dennis.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

replace some 32bit macros with 64bit operations to simplify code
Signed-off-by: NTao Zhou <tao.zhou1@amd.com>
Reviewed-by: NDennis Li <dennis.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

add 64 bits register access functions

v2: implement 64 bit functions in low level
Signed-off-by: NTao Zhou <tao.zhou1@amd.com>
Reviewed-by: NDennis Li <dennis.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

v1: increase ras ce/ue error count
v2: log the number of correctable and uncorrectable errors
Signed-off-by: NTao Zhou <tao.zhou1@amd.com>
Signed-off-by: NHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: NDennis Li <dennis.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

check umc error count in both ras querry function and
ras interrupt handler
Signed-off-by: NHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: NDennis Li <dennis.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

init umc callback function for vega20 in sw early init phase
Signed-off-by: NHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: NDennis Li <dennis.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Implement umc query_ras_error_count function to support querry
both correctable and uncorrectable error
Signed-off-by: NHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: NTao Zhou <tao.zhou1@amd.com>
Reviewed-by: NDennis Li <dennis.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

the change introduces IP headers for unified memory controller (umc)
Signed-off-by: NHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: NDennis Li <dennis.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

remote smu (rsmu) is a sub-block used as ip register interface,
error handling, reset generation.etc
Signed-off-by: NHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: NDennis Li <dennis.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This is common structure as UMC callback function
Signed-off-by: NHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: NDennis Li <dennis.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

the driver needs to program RSMU and UMC registers to
support vega20 RAS feature
Signed-off-by: NHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: NDennis Li <dennis.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

These are common structures that can be included by IP specific
source files
Signed-off-by: NHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: NDennis Li <dennis.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Unused.
Acked-by: NSam Ravnborg <sam@ravnborg.org>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

And fix the fallout.
Acked-by: NSam Ravnborg <sam@ravnborg.org>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

And fix the fallout.
Acked-by: NSam Ravnborg <sam@ravnborg.org>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

And fix up the fallout.
Acked-by: NSam Ravnborg <sam@ravnborg.org>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

And fix the fallout.
Acked-by: NSam Ravnborg <sam@ravnborg.org>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

And fix the fallout.
Acked-by: NSam Ravnborg <sam@ravnborg.org>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Unused.
Acked-by: NSam Ravnborg <sam@ravnborg.org>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Unused.
Acked-by: NSam Ravnborg <sam@ravnborg.org>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Per current logics, the features to enable are determined together
by driver and pptable. This is not efficient in co-debug with
firmware team.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NKenneth Feng <kenneth.feng@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

we should pass irq type, instead of irq client id,
to irq_get/put interface
Signed-off-by: NHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: NFeifei Xu <Feifei.Xu@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

The power limit retrieval should be done per asic. Since we may
need to lookup in the pptable and that's really asic specific.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NKenneth Feng <kenneth.feng@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

There may be 1Mhz delta between target and actual frequency. That
should be taken into consideration for current level check.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NKenneth Feng <kenneth.feng@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Enable arcturus UMD PSTATE support.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NKenneth Feng <kenneth.feng@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Make sure we can still get the accurate gfxclk/uclk/socclk frequency
even on dpm disabled.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NKenneth Feng <kenneth.feng@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

remove redundacy debug log in smu.
eg:
[ 6897.969447] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6897.969448] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6897.969448] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6899.024114] amdgpu: [powerplay] Unsupported SMU message: 38
[ 6899.024151] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6899.024151] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6899.024152] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6900.078296] amdgpu: [powerplay] Unsupported SMU message: 38
[ 6900.078332] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6900.078332] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6900.078333] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6901.133230] amdgpu: [powerplay] Unsupported SMU message: 38
Signed-off-by: NKevin Wang <kevin1.wang@amd.com>
Reviewed-by: NKenneth Feng <kenneth.feng@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Those bitmask prefixed by "SMU_" should be used.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Reviewed-by: NKevin Wang <kevin1.wang@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>