- 25 2月, 2012 1 次提交
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由 Tony Lindgren 提交于
This is needed to minimize io.h so the SoC specific io.h for ARMs can removed. Note that minimal driver changes for DSS and RNG are needed to include cpu.h for SoC detection macros. Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: Matt Mackall <mpm@selenic.com> Cc: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 10 12月, 2011 2 次提交
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由 Peter Ujfalusi 提交于
If the DMA destination position has been asked before the first actual data transfer has been done, the CDAC register still contains 0 (it is initialized to 0 at omsp_dma_start). If CDAC == 0, return the programmed start address. Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com> Reviewed-by: NJarkko Nikula <jarkko.nikula@bitmer.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Peter Ujfalusi 提交于
If the DMA source position has been asked before the first actual data transfer has been done, the CSAC register does not contain valid information. We can identify this situation by checking the CDAC register: CDAC != 0 indicates that the DMA transfer on the channel has been started already. When CDAC == 0 we can not trust the CSAC value since it has not been updated, and can contain random number. Return the start address in case the DMA has not jet started. Note: The CDAC register has been initialized to 0 at dma_start time. Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com> Reviewed-by: NJarkko Nikula <jarkko.nikula@bitmer.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 31 3月, 2011 1 次提交
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由 Lucas De Marchi 提交于
Fixes generated by 'codespell' and manually reviewed. Signed-off-by: NLucas De Marchi <lucas.demarchi@profusion.mobi>
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- 28 1月, 2011 1 次提交
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由 Aaro Koskinen 提交于
Eliminates the following sparse warning: arch/arm/plat-omap/dma.c:137:5: warning: symbol 'omap_dma_in_1510_mode' was not declared. Should it be static? Signed-off-by: NAaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 20 1月, 2011 1 次提交
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由 Adrian Hunter 提交于
When clearing the DMA channel, clear all status bits. When handling a DMA interrupt, clear only the interrupt status bits that have been read and are passed to the channel's interrupt handler, not every status bit. Signed-off-by: NAdrian Hunter <adrian.hunter@nokia.com> Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: NG, Manjunath Kondaiah <manjugk@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 21 12月, 2010 3 次提交
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由 G, Manjunath Kondaiah 提交于
Convert DMA library into DMA platform driver and make use of platform data provided by hwmod data base for OMAP2+ onwards. For OMAP1 processors, the DMA driver in mach-omap uses resource structures for getting platform data. Thanks to Tony Lindgren <tony@atomide.com> for fixing various omap1 issues and testing the same on OSK5912 board. Signed-off-by: NG, Manjunath Kondaiah <manjugk@ti.com> Tested-by: NKevin Hilman <khilman@deeprootsystems.com> Acked-by: NKevin Hilman <khilman@deeprootsystems.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 G, Manjunath Kondaiah 提交于
Implement errata handling to use flags instead of cpu_is_* and cpu_class_* in the code. The errata flags are initialized at init time and during runtime we are using the errata variable (via the IS_DMA_ERRATA macro) to execute the required errata workaround. Reused errata handling patch from: Peter Ujfalusi <peter.ujfalusi@nokia.com> https://patchwork.kernel.org/patch/231191/ Changes to above patch: 1. Changes are done for converting all the existing errata work arounds to use this feature. 2. Detailed description for each errata is added. 3. Fixed bug in SET_DMA_ERRATA macro 4. Bit shifting in macro definitions are replaced with BIT() macro Signed-off-by: NG, Manjunath Kondaiah <manjugk@ti.com> Tested-by: NKevin Hilman <khilman@deeprootsystems.com> Acked-by: NKevin Hilman <khilman@deeprootsystems.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 G, Manjunath Kondaiah 提交于
Prepare DMA library to get converted into DMA driver using platform device model and hwmod infrastucture(for omap2+, resource structures for omap1) The low level read/write macros are replaced with static inline functions and register offsets are handled through static register offset tables mapped through enumeration constants. These low level read/write functions along with static register offset tables will be moved to respective mach-omap dma files in the later patches of this series. There are no functionality changes with these changes except change in logic for handling 16bit registers of OMAP1. Signed-off-by: NG, Manjunath Kondaiah <manjugk@ti.com> Tested-by: NKevin Hilman <khilman@deeprootsystems.com> Acked-by: NKevin Hilman <khilman@deeprootsystems.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 25 11月, 2010 1 次提交
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由 Aaro Koskinen 提交于
Make some functions static to get rid of the following sparse warnings: arch/arm/mach-omap1/mcbsp.c:177:12: warning: symbol 'omap1_mcbsp_init' was not declared. Should it be static? arch/arm/mach-omap1/mux.c:346:22: warning: symbol 'omap1_cfg_reg' was not declared. Should it be static? arch/arm/plat-omap/dma.c:177:5: warning: symbol 'omap_dma_in_1510_mode' was not declared. Should it be static? arch/arm/plat-omap/sram.c:273:12: warning: symbol 'omap1_sram_init' was not declared. Should it be static? Signed-off-by: NAaro Koskinen <aaro.koskinen@nokia.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 06 11月, 2010 1 次提交
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由 Mathias Nyman 提交于
Flush the writes to IRQSTATUS_L0 register in the DMA interrupt handler by reading the register directly after write. This prevents the spurious DMA interrupts noted when using VDD_OPP 1 Signed-off-by: NMathias Nyman <mathias.nyman@nokia.com> Acked-by: NSantosh Shilimkar <Santosh.shilimkar@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 12 10月, 2010 2 次提交
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由 Peter Ujfalusi 提交于
Implement the suggested workaround for OMAP3 regarding to sDMA draining issue, when the channel is disabled on the fly. This errata affects the following configuration: sDMA transfer is source synchronized Buffering is enabled SmartStandby is selected. The issue can be easily reproduced by creating overrun situation while recording audio. Either introduce load to the CPU: nice -19 arecord -D hw:0 -M -B 10000 -F 5000 -f dat > /dev/null & \ dd if=/dev/urandom of=/dev/null or suspending the arecord, and resuming it: arecord -D hw:0 -M -B 10000 -F 5000 -f dat > /dev/null CTRL+Z; fg; CTRL+Z; fg; ... In case of overrun audio stops DMA, and restarts it (without reseting the sDMA channel). When we hit this errata in stop case (sDMA drain did not complete), at the coming start the sDMA will not going to be operational (it is still draining). This leads to DMA stall condition. On OMAP3 we can recover with sDMA channel reset, it has been observed that by introducing unrelated sDMA activity might also help (reading from MMC for example). The same errata exists for OMAP2, where the suggestion is to disable the buffering to avoid this type of error. On OMAP3 the suggestion is to set sDMA to NoStandby before disabling the channel, and wait for the drain to finish, than configure sDMA to SmartStandby again. Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@nokia.com> Acked-by: NJarkko Nikula <jhnikula@gmail.com> Acked-by : Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by : Manjunath Kondaiah G <manjugk@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Jarkko Nikula 提交于
An errata workaround for omap24xx is not setting the buffering disable bit 25 what is the purpose but channel enable bit 7 instead. Background for this fix is the DMA stalling issue with ASoC omap-mcbsp driver. Peter Ujfalusi <peter.ujfalusi@nokia.com> has found an issue in recording that the DMA stall could happen if there were a buffer overrun detected by ALSA and the DMA was stopped and restarted due that. This problem is known to occur on both OMAP2420 and OMAP3. It can recover on OMAP3 after dma free, dma request and reconfiguration cycle. However, on OMAP2420 it seems that only way to recover is a reset. Problem was not visible before the commit c12abc01. That commit changed that the McBSP transmitter/receiver is released from reset only when needed. That is, only enabled McBSP transmitter without transmission was able to prevent this DMA stall problem in receiving side and underlying problem did not show up until now. McBSP transmitter itself seems to no be reason since DMA stall does not recover by enabling the transmission after stall. Debugging showed that there were a DMA write active during DMA stop time and it never completed even when restarting the DMA. Experimenting showed that the DMA buffering disable bit could be used to avoid stalling when using source synchronized transfers. However that could have performance hit and OMAP3 TRM states that buffering disable is not allowed for destination synchronized transfers so subsequent patch will implement a method to complete DMA writes when stopping. This patch is based on assumtion that complete lock-up on OMAP2420 is different but related problem. I don't have access to OMAP2420 errata but I believe this old workaround here is put for a reason but unfortunately a wrong bit was typed and problem showed up only now. Signed-off-by: NJarkko Nikula <jhnikula@gmail.com> Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@nokia.com> Acked-by: NManjunath Kondaiah G <manjugk@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 02 8月, 2010 1 次提交
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由 Samu Onkalo 提交于
Omap DMA controller can prefetch data in advance in case of destination synchronized data transfer. This may increase performance when target HW block doesn't have fifo. Data is waiting for transfer request in DMA fifo instead of read from memory. Signed-off-by: NSamu Onkalo <samu.p.onkalo@nokia.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 21 5月, 2010 2 次提交
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由 manjugk manjugk 提交于
Multi line comments are fixed as per CodingStyle guidelines. Cc: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: NManjunatha GK <manjugk@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Mika Westerberg 提交于
If we are softbooting another kernel using kexec, DMA controller state is not known when we are performing omap_init_dma(). It is possible that some DMA channels are already active. For example after kexec we get: <4>IRQ 0020 for non-allocated DMAchannel 5 <4>IRQ 0020 for non-allocated DMAchannel 5 <4>IRQ 0020 for non-allocated DMAchannel 5 <4>IRQ 0020 for non-allocated DMAchannel 5 <4>IRQ 0020 for non-allocated DMAchannel 5 To prevent any weird things happening, we disable all channel interrupts during init. Signed-off-by: NMika Westerberg <ext-mika.1.westerberg@nokia.com> Acked-by: NKevin Hilman <khilman@deeprootsystems.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 23 4月, 2010 1 次提交
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由 manjugk manjugk 提交于
The register DMA4_CDAC needs to be initialized to zero before starting DMA transfer. Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Govindraj R <govindraj.raja@ti.com> Cc: Kevin Hilman <khilman@deeprootsystems.com> Reported-by: NS, Venkatraman <svenkatr@ti.com> Signed-off-by: NManjunatha GK <manjugk@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 30 3月, 2010 1 次提交
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由 Tejun Heo 提交于
include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h percpu.h is included by sched.h and module.h and thus ends up being included when building most .c files. percpu.h includes slab.h which in turn includes gfp.h making everything defined by the two files universally available and complicating inclusion dependencies. percpu.h -> slab.h dependency is about to be removed. Prepare for this change by updating users of gfp and slab facilities include those headers directly instead of assuming availability. As this conversion needs to touch large number of source files, the following script is used as the basis of conversion. http://userweb.kernel.org/~tj/misc/slabh-sweep.py The script does the followings. * Scan files for gfp and slab usages and update includes such that only the necessary includes are there. ie. if only gfp is used, gfp.h, if slab is used, slab.h. * When the script inserts a new include, it looks at the include blocks and try to put the new include such that its order conforms to its surrounding. It's put in the include block which contains core kernel includes, in the same order that the rest are ordered - alphabetical, Christmas tree, rev-Xmas-tree or at the end if there doesn't seem to be any matching order. * If the script can't find a place to put a new include (mostly because the file doesn't have fitting include block), it prints out an error message indicating which .h file needs to be added to the file. The conversion was done in the following steps. 1. The initial automatic conversion of all .c files updated slightly over 4000 files, deleting around 700 includes and adding ~480 gfp.h and ~3000 slab.h inclusions. The script emitted errors for ~400 files. 2. Each error was manually checked. Some didn't need the inclusion, some needed manual addition while adding it to implementation .h or embedding .c file was more appropriate for others. This step added inclusions to around 150 files. 3. The script was run again and the output was compared to the edits from #2 to make sure no file was left behind. 4. Several build tests were done and a couple of problems were fixed. e.g. lib/decompress_*.c used malloc/free() wrappers around slab APIs requiring slab.h to be added manually. 5. The script was run on all .h files but without automatically editing them as sprinkling gfp.h and slab.h inclusions around .h files could easily lead to inclusion dependency hell. Most gfp.h inclusion directives were ignored as stuff from gfp.h was usually wildly available and often used in preprocessor macros. Each slab.h inclusion directive was examined and added manually as necessary. 6. percpu.h was updated not to include slab.h. 7. Build test were done on the following configurations and failures were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my distributed build env didn't work with gcov compiles) and a few more options had to be turned off depending on archs to make things build (like ipr on powerpc/64 which failed due to missing writeq). * x86 and x86_64 UP and SMP allmodconfig and a custom test config. * powerpc and powerpc64 SMP allmodconfig * sparc and sparc64 SMP allmodconfig * ia64 SMP allmodconfig * s390 SMP allmodconfig * alpha SMP allmodconfig * um on x86_64 SMP allmodconfig 8. percpu.h modifications were reverted so that it could be applied as a separate patch and serve as bisection point. Given the fact that I had only a couple of failures from tests on step 6, I'm fairly confident about the coverage of this conversion patch. If there is a breakage, it's likely to be something in one of the arch headers which should be easily discoverable easily on most builds of the specific arch. Signed-off-by: NTejun Heo <tj@kernel.org> Guess-its-ok-by: NChristoph Lameter <cl@linux-foundation.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
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- 24 2月, 2010 3 次提交
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由 Santosh Shilimkar 提交于
This patch removes all the omap4 specific irq line defines from plat/irqs.h and includes auto-generated irqs-44xx.h All the legacy naming style defines are replaced with the one from irqs-44xx.h Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Reviewed-by: NKevin Hilman <khilman@deeprootsystems.com> Reviewed-by: NPaul Walmsley <paul@pwsan.com> [tony@atomide.com: updated to compile with usb-musb.c] Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Santosh Shilimkar 提交于
The commit 'ba50ea7e' reserves DMA channels 0 and 1 on high security devices, in order to avoid collision between kernel dma transfers and ROM code dma transfers. This fix is applicable only for OMAP3 so add an appropriate check. Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> CC: Kalle Jokiniemi <kalle.jokiniemi@digia.com> CC: Kevin Hilman <khilman@deeprootsystems.com> Reviewed-by: NKevin Hilman <khilman@deeprootsystems.com> Reviewed-by: NPaul Walmsley <paul@pwsan.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Santosh Shilimkar 提交于
This patch enables smart-idle idlemodes and autoidle for sDMA on OMAP4 Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Reviewed-by: NKevin Hilman <khilman@deeprootsystems.com> Reviewed-by: NPaul Walmsley <paul@pwsan.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 16 2月, 2010 1 次提交
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由 Tony Lindgren 提交于
omap: Replace orred CONFIG_ARCH_OMAP2/3/4 with CONFIG_ARCH_OMAP2PLUS Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 20 1月, 2010 1 次提交
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由 Roel Kluin 提交于
The same flag and bits were tested twice. Signed-off-by: NRoel Kluin <roel.kluin@gmail.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 12 12月, 2009 1 次提交
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由 Janusz Krzysztofik 提交于
All of the LCD DMA code in plat-omap/dma.c appears to be OMAP1-only (and apparently only is available on a subset of OMAP1 chips). Move this code to mach-omap1/lcd_dma.c. Tested on OMAP1510 Amstrad Delta. Compile-tested with omap_generic_2420_defconfig. Reported-by: NPaul Walmsley <paul@pwsan.com> Signed-off-by: NJanusz Krzysztofik <jkrzyszt@tis.icnet.pl> Reviewed-by: NPaul Walmsley <paul@pwsan.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 04 12月, 2009 1 次提交
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由 André Goddard Rosa 提交于
That is "success", "unknown", "through", "performance", "[re|un]mapping" , "access", "default", "reasonable", "[con]currently", "temperature" , "channel", "[un]used", "application", "example","hierarchy", "therefore" , "[over|under]flow", "contiguous", "threshold", "enough" and others. Signed-off-by: NAndré Goddard Rosa <andre.goddard@gmail.com> Signed-off-by: NJiri Kosina <jkosina@suse.cz>
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- 12 11月, 2009 4 次提交
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由 Aaro Koskinen 提交于
Clear DMA channel states so that users can assume a known initial state. Signed-off-by: NAaro Koskinen <aaro.koskinen@nokia.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Kalle Jokiniemi 提交于
The secure sram context save uses dma channels 0 and 1. In order to avoid collision between kernel DMA transfers and ROM code dma transfers, we need to reserve DMA channels 0 1 on high security devices. A bug in ROM code leaves dma irq status bits uncleared. Hence those irq status bits need to be cleared when restoring DMA context after off mode. There was also a faulty parameter given to PPA in the secure ram context save assembly code, which caused interrupts to be enabled during secure ram context save. This caused the save to fail sometimes, which resulted the saved context to be corrupted, but also left DMA channels in secure mode. The secure mode DMA channels caused "DMA secure error with device 0" errors to be displayed. Signed-off-by: NKalle Jokiniemi <kalle.jokiniemi@digia.com> Signed-off-by: NJouni Hogander <jouni.hogander@nokia.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Tero Kristo 提交于
For HS/EMU devices, these additional features are also used: - DMA interrupt disable routine added - Added DMA controller reset to DMA context restore Signed-off-by: NTero Kristo <tero.kristo@nokia.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Janusz Krzysztofik 提交于
With CONFIG_PM=y, the omapfb/lcdc device on Amstrad Delta, after initially starting correctly, breaks with the following error messages: omapfb omapfb: resetting (status 0xffffff96,reset count 1) ... omapfb omapfb: resetting (status 0xffffff96,reset count 100) omapfb omapfb: too many reset attempts, giving up. Looking closer at this I have found that it had been broken almost 2 years ago with commit 2418996e3b100114edb2ae110d5d4acb928909d2, PM fixes for OMAP1. The definite reason for broken omapfb/lcdc behavoiur in PM mode appeared to be ARM_IDLECT1:IDLIF_ARM (bit 6) put into idle regardless of LCD DMA possibly running. The bit were set based on return value of the omap_dma_running() function that did not check for dedicated LCD DMA channel status. The patch below fixes this. Note that the hardcoded register value will be fixed during the next merge cycle to use OMAP_LCDC_ defines. Currently the OMAP_LCDC_ defines are local to drivers/video/omap/lcdc.c, so let's not start moving those right now. Created against linux-2.6.32-rc6 Tested on Amstrad Delta Signed-off-by: NJanusz Krzysztofik <jkrzyszt@tis.icnet.pl> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 11 11月, 2009 1 次提交
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由 Tao Hu 提交于
The bug could cause irq enable bit of one DMA channel is cleared/set unexpectedly when 2 (or more) drivers are calling omap_request_dma()/omap_free_dma() simultaneously Signed-off-by: NFei Yang <AFY095@motorola.com> Signed-off-by: NTao Hu <taohu@motorola.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 23 10月, 2009 1 次提交
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由 Santosh Shilimkar 提交于
OMAP sDMA driver API omap_stop_dma() doesn't really stop the dma when used in linking scenario. The DMA channel needs to be disabled before resetting the chain. Also fix clearing of the OMAP_DMA_ACTIVE status in the linked case. Cc: Hari n <hari.zoom@gmail.com> Cc: Jarkko Nikula <jhnikula@gmail.com> Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: NVenkatraman S <svenkatr@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 21 10月, 2009 1 次提交
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由 Tony Lindgren 提交于
Move the remaining headers under plat-omap/include/mach to plat-omap/include/plat. Also search and replace the files using these headers to include using the right path. This was done with: #!/bin/bash mach_dir_old="arch/arm/plat-omap/include/mach" plat_dir_new="arch/arm/plat-omap/include/plat" headers=$(cd $mach_dir_old && ls *.h) omap_dirs="arch/arm/*omap*/ \ drivers/video/omap \ sound/soc/omap" other_files="drivers/leds/leds-ams-delta.c \ drivers/mfd/menelaus.c \ drivers/mfd/twl4030-core.c \ drivers/mtd/nand/ams-delta.c" for header in $headers; do old="#include <mach\/$header" new="#include <plat\/$header" for dir in $omap_dirs; do find $dir -type f -name \*.[chS] | \ xargs sed -i "s/$old/$new/" done find drivers/ -type f -name \*omap*.[chS] | \ xargs sed -i "s/$old/$new/" for file in $other_files; do sed -i "s/$old/$new/" $file done done for header in $(ls $mach_dir_old/*.h); do git mv $header $plat_dir_new/ done Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 20 10月, 2009 1 次提交
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由 Tony Lindgren 提交于
Use ioremap in dma.c Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 15 10月, 2009 1 次提交
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由 Anuj Aggarwal 提交于
Argument tparams was not being used to program global register GCR.HI_THREAD_RESERVED. This patch fixes the same. Signed-off-by: NAnuj Aggarwal <anuj.aggarwal@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 29 8月, 2009 1 次提交
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由 Tony Lindgren 提交于
Search and replace OMAP_IO_ADDRESS with OMAP1_IO_ADDRESS and OMAP2_IO_ADDRESS, and convert omap_read/write into a functions instead of a macros. Also rename OMAP_MPUIO_VBASE to OMAP1_MPUIO_VBASE. In the long run, most code should use ioremap + __raw_read/write instead. Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 25 8月, 2009 1 次提交
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由 Janusz Krzysztofik 提交于
Implement DMA channel self linking on OMAP1510 using AUTO_INIT and REPEAT flags of the DMA CCR register. Created against linux-2.6.31-rc5. Tested on Amstrad Delta. Signed-off-by: NJanusz Krzysztofik <jkrzyszt@tis.icnet.pl> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
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- 10 8月, 2009 1 次提交
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由 Vikram Pandita 提交于
This errata is valid for: OMAP2420 Errata 1.85 Impacts all 2420 ES rev OMAP2430 Errata 1.10 Impacts only ES1.0 Description: DMA may hang when several channels are used in parallel OMAP3430: Not impacted, so remove the errata fix for omap3 Fixed issue reported on cpu_is_omap24xx check reported by Nishant Kamat Signed-off-by: NVikram Pandita <vikram.pandita@ti.com> Reviewed-by: NNishant Kamat <nskamat@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 23 6月, 2009 1 次提交
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由 Kalle Jokiniemi 提交于
This patch enables MStandby smart-idle mode, autoidle smartidle mode, and the autoidle bit for DMA4_OCP_SYSCONFIG. Signed-off-by: NKalle Jokiniemi <ext-kalle.jokiniemi@nokia.com> Signed-off-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NKevin Hilman <khilman@ti.deeprootsystems.com>
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- 29 5月, 2009 2 次提交
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由 Santosh Shilimkar 提交于
This patch adds the support for OMAP4. The platform and machine specific headers and sources updated for OMAP4430 SDP platform. OMAP4430 is Texas Instrument's SOC based on ARM Cortex-A9 SMP architecture. It's a dual core SOC with GIC used for interrupt handling and SCU for cache coherency. Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Santosh Shilimkar 提交于
Original OMAP DMA chaining design had chain_id as one of the callback parameters. Patch 538528de changed it to use logical channel instead. Correct the naming for callback to also use logical channel number instead of the chain_id. More details are on this email thread: http://marc.info/?l=linux-omap&m=122961071931459&w=2Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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