Start using the r8a73a4 PFC on the APE6EVM board
and configure the SCIFA0 console signals in the
PFC via PINCTRL.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

V3 of APE6EVM base board support making use of
1 GiB of memory, the SCIFA0 serial port and
ARM architected timer.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add a DT node for the SMSC 9221 ethernet chip, found on kzm9g, to its
reference implementation.
Signed-off-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add basic Bock-W board support

More devices will be added on top of this patch after
PICNTRL and clock framework are in better shape.
Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Second round of Renesas ARM and SH based SoC pinmux updates for v3.10

Highlights:

* Compilation fixes for sh7269 and for when CONFIG_BUG is not set
* sh-pfc Support for r8a73a4 SoC
* Move GPIOs handling from the PFC device to separate GPIO devices on the r8a7779 SoC

This pull request is based on a merge of:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-pinmux-for-v3.10
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-soc2-for-v3.10

This merge is made to supply run-time dependencies for the following
patches that will bea added on top:

ARM: shmobile: APE6EVM LAN9220 support
ARM: shmobile: APE6EVM PFC support

Remove unused pull-up/down data from the r8a73a4 PFC code.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Function GPIOs are not used anymore, and all code use the GPIO numbers
directly. Remove the GPIOs enumeration.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

All r8a73a4 platforms use the pinctrl API to control pin functions.
Function GPIOs are no longer needed.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Remove IRQ pin function GPIOs that have been deprecated by the pinctrl
API.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Remove SCIF function GPIOs that have been deprecated by the pinctrl API.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

The r8a73a4 board support will use the pinctrl API to control the
external IRQ pins so remove the unused function GPIOS.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

The r8a73a4 board support will use the pinctrl API to control the SCIF
pins, remove the corresponding unused function GPIOS.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

V2 of PINCTRL support for r8a73a4 IRQC hardware
and in particular the external pins IRQ0 -> IRQ57.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add PINCTRL support for r8a73a4 SCIF ports SCIFA0->SCIFA1 and
SCIFB0->SCIFB3.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Implement pull-up/down support for r8a73a4 similar to the implementation
for sh73a0.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

V2 of code to add GPIO -> IRQ mappings to the
PFC table for the r8a73a4 SoC. Requires the IRQs
to be mapped at a fixed location in Linux IRQ
space. The actual IRQs are not handled by the
PFC, instead IRQC is used on r8a73a4.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

The r8a73a4 SoC has sparse GPIO numbers. Declare ranges for pin numbers
in the PFC SoC data. Pin numbers shall be used with the GPIO API from
this point on.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add initial PFC support for the r8a73a4 SoC.

At this point only GPIO interface is supported, move to newer interfaces
planned as incremental changes.

Original authors are Morimoto-san with help from Yoshii-san, thanks to
them for the heavy lifting. Adjusted by Magnus to work together with
updated code in drivers/pinctrl.
Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: NTakashi Yoshii <takashi.yoshii.zj@renesas.com>
Signed-off-by: NMagnus Damm <damm@opensource.se>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

The output pixel clocks can be used without the input pixel clocks.
Split them in different groups.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

GPIOs are now handled by a separate driver, remove GPIO data from the
SoC information structure.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Move GPIOs handling from the PFC device to separate GPIO devices.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

When a GPIO is handled by a separate driver the pinmux
gpio_set_direction() handler won't be called. The pin mux type then need
to be configured to GPIO at request time.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Boards/platforms that register dedicated GPIO devices will not supply a
memory resource for GPIOs. Try to locate the GPIO memory resource at
initialization time, and skip registration of the gpiochip if the
resource can't be found.

This is a temporary modification to ease the transition to separate GPIO
drivers. It should be reverted when all boards and platforms will have
been moved.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

When implemented as a separate IP block, GPIOs should be handled by a
separate driver. To make this possible GPIO support needs to be optional
in the sh-pfc driver.

If no GPIO data registers are supplied in the SoC information structure
skip registration of the gpiochip.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

The target is to get rid of function GPIOs completely. To reach this,
make function GPIOs support optional by skipping the function GPIO chip
registration if no function GPIOS are defined in SoC data.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

The board has 3 LEDs connected to GPIOs. Add a led-gpio device to
support them.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Register the GPIO pin range, and request and free GPIO pins using the
pinctrl API.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

This patch is V3 of a GPIO driver for the R-Car series of
SoCs from Renesas. This driver is designed to be reusable
between multiple SoCs that share the same basic building block,
but so far it has only been used on R-Car H1 (r8a7779).

Each driver instance handles 32 GPIOs with individually
maskable IRQs. The driver operates on a single I/O memory
range and the 32 GPIOs are hooked up a single interrupt.

In the case of R-Car H1 either external IRQ pins or GPIOs
with interrupts can be used for on-board interupts. For
external IRQs 4 pins are supported, and in the case of GPIO
there are 202 GPIOS as 202 interrupts hooked up via 6 driver
instances and to the GIC and the Cortex-A9 Quad.

At this point this driver is interfacing as a regular
platform device driver. In the future DT support will be
submitted as an incremental feature patch.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Function GPIOs are not used anymore, and all code use the GPIO numbers
directly. Remove the GPIOs enumeration.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Refactor the GPIO macro magic to use GPIO numbers directly instead of
the GPIO_GP_x_y enum entries. This will allow removing the GPIO enum
entries from the mach/r8a7779.h header.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

All r8a7779 platforms use the pinctrl API to control functions. Function
GPIOs are unused and unneeded, remove them.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

struct resource is defined in linux/ioport.h. Include it.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

The sh_pfc_phys_to_virt() function ends with a BUG() statement without a
return. When CONFIG_BUG isn't set the function will thus have no return
value. Fix it.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Conflicts:
	drivers/pinctrl/sh-pfc/pfc-r8a7740.c

This merge is to provide r8a73a4 SoC files, which are added in the
soc branch and depended on by r8a73a4 pfc-changes which are to
be added to the pinmux branch.

The r8a7790 SoC supports LPAE and has memory window up to
0x2ffffffff. Convert to 64-bit addresses by enlarging
#addr-cells and #size-cells to 2.
Signed-off-by: NTakashi Yoshii <takashi.yoshii.zj@renesas.com>
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

The r8a73a4 SoC supports LPAE and has memory window up to
0x2ffffffff. Convert to 64-bit addresses by enlarging
#addr-cells and #size-cells to 2.
Signed-off-by: NTakashi Yoshii <takashi.yoshii.zj@renesas.com>
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add a platform device for the r8a7790 PFC.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add IRQC interrupt controller support to r8a7790 by
hooking up a single IRQC instances to handle 4 external
IRQ signals. The IRQC controller is tied to SPIs of
the GIC. On r8a7790 the external IRQ pins routing is
handled by the PFC which is excluded from this patch.

Both platform devices and DT devices are added in this
patch. The platform device versions are used to provide
a static interrupt map configuration for board code
written in C.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add SCIF serial port support to the r8a7790 SoC by
adding platform devices for SCIFA0 -> SCIFA2 as well
as SCIFB0 -> SCIFB2 and SCIF0 -> SCIF1 together with
clock bindings. DT device description is excluded at
this point since such bindings are still under
development.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add initial support for the r8a7790 SoC including:
 - Single Cortex-A15 CPU Core
 - GIC
 - Architecture timer

No static virtual mappings are used, all the components
make use of ioremap(). DT_MACHINE_START is still wrapped
in CONFIG_USE_OF to match other mach-shmobile code.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>