1. 10 11月, 2021 2 次提交
    • V
      drm/i915: Use vblank workers for gamma updates · 2bbc6fca
      Ville Syrjälä 提交于
      The pipe gamma registers are single buffered so they should only
      be updated during the vblank to avoid screen tearing. In fact they
      really should only be updated between start of vblank and frame
      start because that is the only time the pipe is guaranteed to be
      empty. Already at frame start the pipe begins to fill up with
      data for the next frame.
      
      Unfortunately frame start happens ~1 scanline after the start
      of vblank which in practice doesn't always leave us enough time to
      finish the gamma update in time (gamma LUTs can be several KiB of
      data we have to bash into the registers). However we must try our
      best and so we'll add a vblank work for each pipe from where we
      can do the gamma update. Additionally we could consider pushing
      frame start forward to the max of ~4 scanlines after start of
      vblank. But not sure that's exactly a validated configuration.
      As it stands the ~100 first pixels tend to make it through with
      the old gamma values.
      
      Even though the vblank worker is running on a high prority thread
      we still have to contend with C-states. If the CPU happens be in
      a deep C-state when the vblank interrupt arrives even the irq
      handler gets delayed massively (I've observed dozens of scanlines
      worth of latency). To avoid that problem we'll use the qos mechanism
      to keep the CPU awake while the vblank work is scheduled.
      
      With all this hooked up we can finally enjoy near atomic gamma
      updates. It even works across several pipes from the same atomic
      commit which previously was a total fail because we did the
      gamma updates for each pipe serially after waiting for all
      pipes to have latched the double buffered registers.
      
      In the future the DSB should take over this responsibility
      which will hopefully avoid some of these issues.
      
      Kudos to Lyude for finishing the actual vblank workers.
      Works like the proverbial train toilet.
      
      v2: Add missing intel_atomic_state fwd declaration
      v3: Clean up properly when not scheduling the worker
      v4: Clean up the rest and add tracepoints
      v5: s/intel_wait_for_vblank_works/intel_wait_for_vblank_workers/ (Jani,Uma)
      
      CC: Lyude Paul <lyude@redhat.com>
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20211020223339.669-4-ville.syrjala@linux.intel.comReviewed-by: NUma Shankar <uma.shankar@intel.com>
      2bbc6fca
    • V
      drm/i915: Do vrr push before sampling the frame counter · 6f9976bd
      Ville Syrjälä 提交于
      Do the vrr push before we sample the frame counter to
      know when the commit has been latched. Doing these in the
      wrong order could lead us to complete the flip before it
      has actually happened.
      
      Cc: Manasi Navare <manasi.d.navare@intel.com>
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20211020223339.669-3-ville.syrjala@linux.intel.comReviewed-by: NUma Shankar <uma.shankar@intel.com>
      6f9976bd
  2. 09 11月, 2021 2 次提交
  3. 06 11月, 2021 1 次提交
  4. 05 11月, 2021 6 次提交
  5. 04 11月, 2021 18 次提交
  6. 03 11月, 2021 10 次提交
  7. 02 11月, 2021 1 次提交