- 21 2月, 2011 2 次提交
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由 Dima Zavin 提交于
Add a new 'reset' clk op. This can be provided for any clock, not just peripherals. Signed-off-by: NDima Zavin <dima@android.com> Acked-by: NOlof Johansson <olof@lixom.net> Signed-off-by: NColin Cross <ccross@android.com>
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由 Stephen Warren 提交于
Signed-off-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NColin Cross <ccross@android.com>
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- 10 2月, 2011 2 次提交
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由 Colin Cross 提交于
Save and restore pll and osc state during suspend Add digital audio clocks Update clk dev associations Correct max clock frequencies Add pll_p as additional cpu clock state Add values to plld table Fix register offset for sdmmc4 clock Add blink timer to tegra2_clocks Signed-off-by: NColin Cross <ccross@android.com>
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由 Colin Cross 提交于
Signed-off-by: NColin Cross <ccross@android.com>
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- 26 11月, 2010 1 次提交
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factorise some generic infrastructure to assist looking up struct clks for the ARM & SH architecture. as the code is identical at 99% put the arch specific code for allocation as example in asm/clkdev.h Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: NPaul Mundt <lethal@linux-sh.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 22 10月, 2010 2 次提交
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由 Mike Rapoport 提交于
Signed-off-by: NMike Rapoport <mike@compulab.co.il> CC: Gary King <GKing@nvidia.com> Signed-off-by: NColin Cross <ccross@android.com>
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由 Colin Cross 提交于
- Add drivers to clock lookup table - Add new pll_m entries - Support I2C U16 divider - Fix rate reporting on 32.768kHz clock - Call propagate rate only if set_rate succeeds - Add support for audio_sync clock - Add 24MHz to PLLA frequency list - Correct i2s1/2/spdifout mux - Add suspend support - Fix enable/disable parent clocks in set_parent - Add max_rate parameter to all clocks - DVFS support - Add virtual cpu clock with dvfs - Support clk_round_rate - Fix requesting very high periph frequencies - Add quirks for PLLU: PLLU is slightly different from the rest of the PLLs. The lock enable bit is at bit 22 instead of 18 in the MISC register, and the post divider field is a single bit with reversed values from other PLLs. - Simplify recalculating clock rates - Fix UART divider flags - Remove unused clock ops Signed-off-by: NColin Cross <ccross@android.com>
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- 06 8月, 2010 1 次提交
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由 Colin Cross 提交于
v2: fixes from Russell King: - include linux/io.h instead of asm/io.h - fix whitespace in Kconfig - Use spin_lock_init to initialize lock - Return -ENOSYS instead of BUG for unimplemented clock ops - Use proper return values in tegra2 clock ops additional changes: - Rename some clocks to match dev_ids - add rate propagation - add debugfs entries - add support for clock listed in clk_lookup under multiple dev_ids v3: - Replace per-clock locking with global clock lock - Autodetect clock state on init - Let clock dividers pick next lower possible frequency - Add support for clock init tables - Minor bug fixes - Fix checkpatch issues Signed-off-by: NColin Cross <ccross@android.com>
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