The pcm driver name has been changed, but the device name has not.
Signed-off-by: NScott Jiang <scott.jiang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

No one uses this func, so just punt it.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Do not trace arch_local_save_flags(), arch_local_irq_*() and friends.
Although they are marked inline, gcc may still make a function out of
them and add it to the pool of functions that are traced by the function
tracer. This can cause undesirable results (kernel panic, triple faults,
etc).

Add the notrace notation to prevent them from ever being traced.
Signed-off-by: NSteven Rostedt <rostedt@goodmis.org>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The bug in the BF526 rom when doing a software reset exists only in older
silicon versions, so don't clear SWRST on newer parts.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The BF51x's alternative portmux Kconfig options were copy & pasted from
the BF52x, but never tweaked to reflect it.  So drop the old options as
they were never used (and were simply wrong), and add the BF51x specific
pieces to the Kconfig and header.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Back in commit c03c2a87, we fixed logic in the non-bf54x
GPIO resume code to set the data levels properly before the direction
to avoid spurious line glitches.  But we missed the bf54x code paths.
So add the same fix there.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

No need to reload these registers constantly since they're always
available (we're not making any function calls in between).
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The Blackfin C ABI says we do not need to save/restore R0-R3 and P0-P2
as they are available as scratch registers.  So don't bother.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Re-architect how we save/restore the gpio/port logic that only pertains
to bf538/bf539 parts by pulling it out of the core code paths and pushing
it out to bf538-specific locations.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The current save logic used in hibernation is to do a MMR load (base +
offset) into a register, and then push that onto the stack.  Then when
restoring, pop off the stack into a register followed by a MMR store
(base + offset).  These use plenty of 32bit insns rather than 16bit,
are pretty long winded, and full of pipeline bubbles.

So, by taking advantage of MMRs that are contiguous, the multi-register
push/pop insn, and register abuse, we can shrink this code considerably.

When saving, the new logic does a lot of loads into the data and pointer
registers before executing a single multi-register push insn.  Then when
restoring, we do a single multi-register pop insn followed by a lot of
stores.  Overall, this allows us to cut the insn count by ~30%, the code
size by ~45%, and drastically reduce the register hazards that trigger
bubbles in the pipeline.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

EVT0 is for emulation, EVT1 is for reset, and EVT4 is the "global int
disable" region.  None of these are used by software (or even hardware),
so don't bother saving/restoring them when we hibernate since nothing
ever uses these in Linux (the only thing they would be useful for is
core-memory scratch, but that's just crazy talk).
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

This defines only get used in the hibernate code, so remove them from the
global dpmc header as no one else cares.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The RETE/RETN registers are only used in emulation(JTAG) and NMI nodes,
or as scratch registers, neither of which need to be saved/restored as
this code doesn't execute at those core event levels.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

For parts with more than one SIC_IWR, we can optimize the writing
a little bit using better Blackfin insns.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Have the logic that uses peripheral interrupt blocks key off of pint
defines rather than CPU names so that things are generalized across
families.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Have the code work off of MMR names rather than CPU defines so there is
less code to tweak in the future with new parts.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Don't bind the code to specific CPU defines.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

We have a struct in the headers describing the register layout, so
drop the local duplicate one.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The hardware block uses the name "request" rather than "irq", so update
the struct accordingly.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The array of pointers to register blocks never changes, so constify it.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

These defines don't accomplish much as GPIO_# is the same thing as #.
Each CPU already provides helpful symbolic defines like GPIO_<PIN>
which everyone uses, so just punt these # ones.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Not sure how these guys slipped in, but they're annoying me.
So bring these unicode space gremlins down to earth to normal
ascii spaces.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

For now, this only supports gptimers.  Support for dedicated PWM devices
as found on newer parts to come.
Signed-off-by: NMichael Hennerich <michael.hennerich@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The API is geared around timer ids, except for the act of enabling
and disabling timers.  So add a small helper to fill out the gap.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The alignment is normally handled by PERCPU(), but we need to do it
ourselves in the XIP build due to the custom layout.
Signed-off-by: NSteven Miao <realmz6@gmail.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Use proper helper macros for reading/writing the MMRs rather than
volatile markings on the struct.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Now that asm/gptimers.h has the hardware register struct layout, there's
no need to duplicate things locally.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Passing a non-simple expression in as the addr arg could incorrectly
apply the pointer cast resulting in misbehavior.  Add proper paren.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The address limit is already set in flush_old_exec() so this
set_fs(USER_DS) is redundant.
Signed-off-by: NMathias Krause <minipli@googlemail.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

These flashes are always on the board, so might as well enable them by
default rather than a module.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The documentation for the IMDMA channels appears to be incorrect.
These DMA blocks don't actually have PERIPHERAL_MAP MMRs for us
to access.  Attempts to do so lead to system mmr hardware errors.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The Blackfin mutex.h is merely a copy of an older asm-generic/mutex-dec.h,
so punt it and just use the common one directly.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

This moves the double fault data used at boot time into a single struct
which can then easily be addressed with indexed loads rather than having
to explicitly load multiple addresses.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

This just imports all of the optimization work done in the
common startup code.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The default for the Blackfin SPI driver is 8 bits and dma disabled,
so many of the bfin5xx_spi_chip resources are redundant.  So punt
those parts.

Further, drivers should themselves be declaring 16 bit transfers,
so for those that do, and for the ones which no longer do 16 bit
transfers, drop the bfin5xx_spi_chip resources.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>