1. 22 4月, 2020 1 次提交
    • Y
      net: mscc: ocelot: move ocelot ptp clock code out of ocelot.c · 2b49d128
      Yangbo Lu 提交于
      The Ocelot PTP clock driver had been embedded into ocelot.c driver.
      It had supported basic gettime64/settime64/adjtime/adjfine functions
      by now which were used by both Ocelot switch and Felix switch.
      
      This patch is to move current ptp clock code out of ocelot.c driver
      maintaining as a single ocelot_ptp.c.
      For futher new features implementation, the common code could be put
      in ocelot_ptp.c and the switch specific code should be in specific
      switch driver. The interrupt implementation in SoC is different
      between Ocelot and Felix.
      Signed-off-by: NYangbo Lu <yangbo.lu@nxp.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      2b49d128
  2. 16 4月, 2020 1 次提交
    • V
      net: mscc: ocelot: fix untagged packet drops when enslaving to vlan aware bridge · 87b0f983
      Vladimir Oltean 提交于
      To rehash a previous explanation given in commit 1c44ce56 ("net:
      mscc: ocelot: fix vlan_filtering when enslaving to bridge before link is
      up"), the switch driver operates the in a mode where a single VLAN can
      be transmitted as untagged on a particular egress port. That is the
      "native VLAN on trunk port" use case.
      
      The configuration for this native VLAN is driven in 2 ways:
       - Set the egress port rewriter to strip the VLAN tag for the native
         VID (as it is egress-untagged, after all).
       - Configure the ingress port to drop untagged and priority-tagged
         traffic, if there is no native VLAN. The intention of this setting is
         that a trunk port with no native VLAN should not accept untagged
         traffic.
      
      Since both of the above configurations for the native VLAN should only
      be done if VLAN awareness is requested, they are actually done from the
      ocelot_port_vlan_filtering function, after the basic procedure of
      toggling the VLAN awareness flag of the port.
      
      But there's a problem with that simplistic approach: we are trying to
      juggle with 2 independent variables from a single function:
       - Native VLAN of the port - its value is held in port->vid.
       - VLAN awareness state of the port - currently there are some issues
         here, more on that later*.
      The actual problem can be seen when enslaving the switch ports to a VLAN
      filtering bridge:
       0. The driver configures a pvid of zero for each port, when in
          standalone mode. While the bridge configures a default_pvid of 1 for
          each port that gets added as a slave to it.
       1. The bridge calls ocelot_port_vlan_filtering with vlan_aware=true.
          The VLAN-filtering-dependent portion of the native VLAN
          configuration is done, considering that the native VLAN is 0.
       2. The bridge calls ocelot_vlan_add with vid=1, pvid=true,
          untagged=true. The native VLAN changes to 1 (change which gets
          propagated to hardware).
       3. ??? - nobody calls ocelot_port_vlan_filtering again, to reapply the
          VLAN-filtering-dependent portion of the native VLAN configuration,
          for the new native VLAN of 1. One can notice that after toggling "ip
          link set dev br0 type bridge vlan_filtering 0 && ip link set dev br0
          type bridge vlan_filtering 1", the new native VLAN finally makes it
          through and untagged traffic finally starts flowing again. But
          obviously that shouldn't be needed.
      
      So it is clear that 2 independent variables need to both re-trigger the
      native VLAN configuration. So we introduce the second variable as
      ocelot_port->vlan_aware.
      
      *Actually both the DSA Felix driver and the Ocelot driver already had
      each its own variable:
       - Ocelot: ocelot_port_private->vlan_aware
       - Felix: dsa_port->vlan_filtering
      but the common Ocelot library needs to work with a single, common,
      variable, so there is some refactoring done to move the vlan_aware
      property from the private structure into the common ocelot_port
      structure.
      
      Fixes: 97bb69e1 ("net: mscc: ocelot: break apart ocelot_vlan_port_apply")
      Signed-off-by: NVladimir Oltean <vladimir.oltean@nxp.com>
      Reviewed-by: NHoratiu Vultur <horatiu.vultur@microchip.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      87b0f983
  3. 28 3月, 2020 1 次提交
  4. 15 3月, 2020 1 次提交
  5. 10 3月, 2020 1 次提交
    • V
      net: mscc: ocelot: properly account for VLAN header length when setting MRU · a8015ded
      Vladimir Oltean 提交于
      What the driver writes into MAC_MAXLEN_CFG does not actually represent
      VLAN_ETH_FRAME_LEN but instead ETH_FRAME_LEN + ETH_FCS_LEN. Yes they are
      numerically equal, but the difference is important, as the switch treats
      VLAN-tagged traffic specially and knows to increase the maximum accepted
      frame size automatically. So it is always wrong to account for VLAN in
      the MAC_MAXLEN_CFG register.
      
      Unconditionally increase the maximum allowed frame size for
      double-tagged traffic. Accounting for the additional length does not
      mean that the other VLAN membership checks aren't performed, so there's
      no harm done.
      
      Also, stop abusing the MTU name for configuring the MRU. There is no
      support for configuring the MRU on an interface at the moment.
      
      Fixes: a556c76a ("net: mscc: Add initial Ocelot switch support")
      Fixes: fa914e9c ("net: mscc: ocelot: create a helper for changing the port MTU")
      Signed-off-by: NVladimir Oltean <vladimir.oltean@nxp.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      a8015ded
  6. 05 3月, 2020 1 次提交
    • V
      net: mscc: ocelot: eliminate confusion between CPU and NPI port · 69df578c
      Vladimir Oltean 提交于
      Ocelot has the concept of a CPU port. The CPU port is represented in the
      forwarding and the queueing system, but it is not a physical device. The
      CPU port can either be accessed via register-based injection/extraction
      (which is the case of Ocelot), via Frame-DMA (similar to the first one),
      or "connected" to a physical Ethernet port (called NPI in the datasheet)
      which is the case of the Felix DSA switch.
      
      In Ocelot the CPU port is at index 11.
      In Felix the CPU port is at index 6.
      
      The CPU bit is treated special in the forwarding, as it is never cleared
      from the forwarding port mask (once added to it). Other than that, it is
      treated the same as a normal front port.
      
      Both Felix and Ocelot should use the CPU port in the same way. This
      means that Felix should not use the NPI port directly when forwarding to
      the CPU, but instead use the CPU port.
      
      This patch is fixing this such that Felix will use port 6 as its CPU
      port, and just use the NPI port to carry the traffic.
      
      Therefore, eliminate the "ocelot->cpu" variable which was holding the
      index of the NPI port for Felix, and the index of the CPU port module
      for Ocelot, so the variable was actually configuring different things
      for different drivers and causing at least part of the confusion.
      
      Also remove the "ocelot->num_cpu_ports" variable, which is the result of
      another confusion. The 2 CPU ports mentioned in the datasheet are
      because there are two frame extraction channels (register based or DMA
      based). This is of no relevance to the driver at the moment, and
      invisible to the analyzer module.
      Signed-off-by: NVladimir Oltean <vladimir.oltean@nxp.com>
      Suggested-by: NAllan W. Nielsen <allan.nielsen@microchip.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      69df578c
  7. 04 3月, 2020 2 次提交
  8. 06 1月, 2020 1 次提交
  9. 04 12月, 2019 1 次提交
    • V
      net: mscc: ocelot: unregister the PTP clock on deinit · 9385973f
      Vladimir Oltean 提交于
      Currently a switch driver deinit frees the regmaps, but the PTP clock is
      still out there, available to user space via /dev/ptpN. Any PTP
      operation is a ticking time bomb, since it will attempt to use the freed
      regmaps and thus trigger kernel panics:
      
      [    4.291746] fsl_enetc 0000:00:00.2 eth1: error -22 setting up slave phy
      [    4.291871] mscc_felix 0000:00:00.5: Failed to register DSA switch: -22
      [    4.308666] mscc_felix: probe of 0000:00:00.5 failed with error -22
      [    6.358270] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000088
      [    6.367090] Mem abort info:
      [    6.369888]   ESR = 0x96000046
      [    6.369891]   EC = 0x25: DABT (current EL), IL = 32 bits
      [    6.369892]   SET = 0, FnV = 0
      [    6.369894]   EA = 0, S1PTW = 0
      [    6.369895] Data abort info:
      [    6.369897]   ISV = 0, ISS = 0x00000046
      [    6.369899]   CM = 0, WnR = 1
      [    6.369902] user pgtable: 4k pages, 48-bit VAs, pgdp=00000020d58c7000
      [    6.369904] [0000000000000088] pgd=00000020d5912003, pud=00000020d5915003, pmd=0000000000000000
      [    6.369914] Internal error: Oops: 96000046 [#1] PREEMPT SMP
      [    6.420443] Modules linked in:
      [    6.423506] CPU: 1 PID: 262 Comm: phc_ctl Not tainted 5.4.0-03625-gb7b2a5dadd7f #204
      [    6.431273] Hardware name: LS1028A RDB Board (DT)
      [    6.435989] pstate: 40000085 (nZcv daIf -PAN -UAO)
      [    6.440802] pc : css_release+0x24/0x58
      [    6.444561] lr : regmap_read+0x40/0x78
      [    6.448316] sp : ffff800010513cc0
      [    6.451636] x29: ffff800010513cc0 x28: ffff002055873040
      [    6.456963] x27: 0000000000000000 x26: 0000000000000000
      [    6.462289] x25: 0000000000000000 x24: 0000000000000000
      [    6.467617] x23: 0000000000000000 x22: 0000000000000080
      [    6.472944] x21: ffff800010513d44 x20: 0000000000000080
      [    6.478270] x19: 0000000000000000 x18: 0000000000000000
      [    6.483596] x17: 0000000000000000 x16: 0000000000000000
      [    6.488921] x15: 0000000000000000 x14: 0000000000000000
      [    6.494247] x13: 0000000000000000 x12: 0000000000000000
      [    6.499573] x11: 0000000000000000 x10: 0000000000000000
      [    6.504899] x9 : 0000000000000000 x8 : 0000000000000000
      [    6.510225] x7 : 0000000000000000 x6 : ffff800010513cf0
      [    6.515550] x5 : 0000000000000000 x4 : 0000000fffffffe0
      [    6.520876] x3 : 0000000000000088 x2 : ffff800010513d44
      [    6.526202] x1 : ffffcada668ea000 x0 : ffffcada64d8b0c0
      [    6.531528] Call trace:
      [    6.533977]  css_release+0x24/0x58
      [    6.537385]  regmap_read+0x40/0x78
      [    6.540795]  __ocelot_read_ix+0x6c/0xa0
      [    6.544641]  ocelot_ptp_gettime64+0x4c/0x110
      [    6.548921]  ptp_clock_gettime+0x4c/0x58
      [    6.552853]  pc_clock_gettime+0x5c/0xa8
      [    6.556699]  __arm64_sys_clock_gettime+0x68/0xc8
      [    6.561331]  el0_svc_common.constprop.2+0x7c/0x178
      [    6.566133]  el0_svc_handler+0x34/0xa0
      [    6.569891]  el0_sync_handler+0x114/0x1d0
      [    6.573908]  el0_sync+0x140/0x180
      [    6.577232] Code: d503201f b00119a1 91022263 b27b7be4 (f9004663)
      [    6.583349] ---[ end trace d196b9b14cdae2da ]---
      [    6.587977] Kernel panic - not syncing: Fatal exception
      [    6.593216] SMP: stopping secondary CPUs
      [    6.597151] Kernel Offset: 0x4ada54400000 from 0xffff800010000000
      [    6.603261] PHYS_OFFSET: 0xffffd0a7c0000000
      [    6.607454] CPU features: 0x10002,21806008
      [    6.611558] Memory Limit: none
      
      And now that ocelot->ptp_clock is checked at exit, prevent a potential
      error where ptp_clock_register returned a pointer-encoded error, which
      we are keeping in the ocelot private data structure. So now,
      ocelot->ptp_clock is now either NULL or a valid pointer.
      
      Fixes: 4e3b0468 ("net: mscc: PTP Hardware Clock (PHC) support")
      Cc: Antoine Tenart <antoine.tenart@bootlin.com>
      Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: NVladimir Oltean <vladimir.oltean@nxp.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      9385973f
  10. 28 11月, 2019 2 次提交
  11. 22 11月, 2019 3 次提交
  12. 16 11月, 2019 7 次提交
  13. 12 11月, 2019 15 次提交
  14. 07 11月, 2019 2 次提交
  15. 30 10月, 2019 1 次提交
    • V
      net: mscc: ocelot: refuse to overwrite the port's native vlan · b9cd75e6
      Vladimir Oltean 提交于
      The switch driver keeps a "vid" variable per port, which signifies _the_
      VLAN ID that is stripped on that port's egress (aka the native VLAN on a
      trunk port).
      
      That is the way the hardware is designed (mostly). The port->vid is
      programmed into REW:PORT:PORT_VLAN_CFG:PORT_VID and the rewriter is told
      to send all traffic as tagged except the one having port->vid.
      
      There exists a possibility of finer-grained egress untagging decisions:
      using the VCAP IS1 engine, one rule can be added to match every
      VLAN-tagged frame whose VLAN should be untagged, and set POP_CNT=1 as
      action. However, the IS1 can hold at most 512 entries, and the VLANs are
      in the order of 6 * 4096.
      
      So the code is fine for now. But this sequence of commands:
      
      $ bridge vlan add dev swp0 vid 1 pvid untagged
      $ bridge vlan add dev swp0 vid 2 untagged
      
      makes untagged and pvid-tagged traffic be sent out of swp0 as tagged
      with VID 1, despite user's request.
      
      Prevent that from happening. The user should temporarily remove the
      existing untagged VLAN (1 in this case), add it back as tagged, and then
      add the new untagged VLAN (2 in this case).
      
      Cc: Antoine Tenart <antoine.tenart@bootlin.com>
      Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
      Fixes: 7142529f ("net: mscc: ocelot: add VLAN filtering")
      Signed-off-by: NVladimir Oltean <olteanv@gmail.com>
      Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com>
      Acked-by: NAlexandre Belloni <alexandre.belloni@bootlin.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      b9cd75e6