* Clearing IRQ from ata_sff_error_handler() is necessary only when the
  port is gonna be thawed before performing EH actions and some
  controllers don't like being accessed after certain failure modes
  until they're reset.  Clear IRQ iff the port is being thawed.

* When the controller succesfully indicated bus error, the point of
  thawing doesn't matter.  Move thawing inside bmdma part of EH.  This
  is a bit ugly but will ease code reorganization later.

* Remove the unneeded ata_sff_sync().
Signed-off-by: NTejun Heo <tj@kernel.org>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

sata_mv initializes unused ioports fields including bmdma_addr to
NULL.  As later changes will conditionalize BMDMA, this makes sata_mv
unnecessarily dependent on BMDMA.  Remove the unnecessary
initialization.
Signed-off-by: NTejun Heo <tj@kernel.org>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

sata_inic162x no longer uses SFF interface.  Move it out of
CONFIG_ATA_SFF.
Signed-off-by: NTejun Heo <tj@kernel.org>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

pata_sch is standard SFF.  No reason to open code init.  Use
ata_pci_sff_init_one() instead.
Signed-off-by: NTejun Heo <tj@kernel.org>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

Use our own mmio area to avoid PCI posting. This avoids the rather slow
paranoid implementation in the default handler.
Signed-off-by: NAlan Cox <alan@linux.intel.com>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

We don't need to stall and wait after loading the task file and before
issuing a command, so don't do it. This shows up on profiles and is not
needed.
Signed-off-by: NAlan Cox <alan@linux.intel.com>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

sata_nv was incorrectly using ata_host_activate() instead of
ata_pci_sff_activate_host() leading to IRQ assignment failure in
legacy mode.  Fix it.
Signed-off-by: NTejun Heo <tj@kernel.org>
Cc: Robert Hancock <hancockr@shaw.ca>
Cc: stable@kernel.org
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

page_mapping() check this via VM_BUG_ON(PageSlab(page)) so we bug here
with the according debuging turned on.

Future TODO: replace this with a flush_dcache_page_for_pio() API
Signed-off-by: NSebastian Andrzej Siewior <sebastian@breakpoint.cc>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>
Cc: stable@kernel.org

cmd640_hardware_init() reads CFR but doesn't use the value read...
Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

Now, with the introduction of the sff_set_devctl() method, we can
use it in sff_irq_on() method too -- that way its implementations
in 'pata_bf54x' and 'pata_scc' become virtually identical to
ata_sff_irq_on().  The sff_irq_on() method now becomes quite
superfluous, and the only reason not to remove it completely is
the existence of the 'pata_octeon_cf' driver which implements it
as an empty function. Just make the method optional then, with
ata_sff_irq_on() becoming generic taskfile-bound function, still
global for the 'pata_bf54x' driver to be able to call it from its
thaw() and postreset() methods.

While at it, make the sff_irq_on() method and ata_sff_irq_on() return
'void' as the result is always ignored anyway.
Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

The set of libata's taskfile access methods is clearly incomplete as
it lacks a method to write to the device control register -- which
forces drivers like 'pata_bf54x' and 'pata_scc' to implement more
"high level" (and more weighty) methods like freeze() and postreset().

So, introduce the optional sff_set_devctl() method which the drivers
only have to implement if the standard iowrite8() can't be used (just
like the existing sff_check_altstatus() method) and make use of it
in the freeze() and postreset() method implementations (I could also
have used it in softreset() method but it also reads other taskfile
registers without using tf_read() making that quite pointless);
this makes freeze() method implementations in the 'pata_bf54x' and
'pata_scc' methods virtually identical to ata_sff_freeze(), so we
can get rid of them completely.
Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

Add "em_buffer" attribute for SATA AHCI hosts to provide a way for
userland to access AHCI EM (enclosure management) buffer directly if the
host supports EM.

AHCI driver should support SGPIO EM messages. However the SATA/AHCI
specs did not define the SGPIO message format filled in EM buffer.
Different HW vendors may have different definitions. The mainly purpose
of this attribute is to solve this issue by allowing HW vendors to
provide userland drivers and tools for their SGPIO initiators.
Signed-off-by: NHarry Zhang <harry.zhang@amd.com>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

Detect enclosure management message type automatically at driver
initialization, instead of using module parameter "ahci_em_messages".
Signed-off-by: NHarry Zhang <harry.zhang@amd.com>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

The device control register exists and its address is set by scc_setup_ports(),
hence the check is useless...
Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

... since, of course, it's not used outside this driver.
Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

Use __ratelimit() instead of its own private rate limit implementation.
Signed-off-by: NAkinobu Mita <akinobu.mita@gmail.com>
Cc: Jeff Garzik <jgarzik@pobox.com>
Cc: linux-ide@vger.kernel.org
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

There are some SATA devices which take relatively long to get out of
0xff status after reset.  In libata, this timeout is determined by
ATA_TMOUT_FF_WAIT.  Quantum GoVault is the worst requring about 2s for
reliable detection.  However, because 2s 0xff timeout can introduce
rather long spurious delay during boot, libata has been compromising
at the next longest timeout of 800ms for HHD424020F7SV00 iVDR drive.

Now that parallel scan is in place for common drivers, libata can
afford 2s 0xff timeout.  Use 2s 0xff timeout if parallel scan is
enabled.

Please note that the chance of spurious wait is pretty slim w/ working
SCR access so this will only affect SATA controllers w/o SCR access
which isn't too common these days.

Please read the following thread for more information on the GoVault
drive.

  http://thread.gmane.org/gmane.linux.ide/14545/focus=14663Signed-off-by: NTejun Heo <tj@kernel.org>
Cc: Gary Hade <garyhade@us.ibm.com>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

... since I see no callers of it.
Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

In 2009, While running "cache read" performance test of drives behind
SII PMP we encountered a "all 5 drives" timeout on more than 30% of the
machines under test.  This patch reduces the rate by a factor of about 70.
Low enough that we didn't care to further investigate the issue.

Performance impact with any sort of "normal" use was ~2%+ CPU and less
than 1% throughput degradation.  Worst case impact (cached read) was
6% IOPS reduction. This is with NCQ off (q=1) but I believe FIS based
switching enabled in the SATA driver.

The patch disables "Early ACK" in the 3726 port multiplier.
"Early ACK" is issued when device sends a FIS to the host (via PMP)
and the PMP sends an ACK immediately back to the device - well before
the host gets the response. Under worst case IOPs load (cached read
test) and more than 2 PMPs connected to a 4-port SATA controller,
I suspect the time to service all of the PMPs is exceeding the PMPs
ability to keep track of outstanding FIS it owes the Host. Reducing
the number of PMPs to 2 (or 1) reduces the frequency by several orders
of magnitude. Kudos to Gwendal for initial debugging of this issue.
[Any errors in the description are mine, not his.]

Patch is currently in production on Google servers.
Signed-off-by: NGrant Grundler <grundler@google.com>
Signed-off-by: NGwendal Grignou <gwendal@google.com>
Acked-by: NTejun Heo <tj@kernel.org>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

Implicit slab.h inclusion via percpu.h is about to go away.  Make sure
gfp.h or slab.h is included as necessary.
Signed-off-by: NTejun Heo <tj@kernel.org>
Cc: Stephen Rothwell <sfr@canb.auug.org.au>
Cc: Jeff Garzik <jgarzik@pobox.com>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

It turns out different generations of MCPs have differing quirks.

* MCP 65-73 : FPDMA AA broken, lies about PMP support, forgets to report NCQ
* MCP 77-79 : FPDMA AA broken, lies about PMP support
* MCP 89    : FPDMA AA broken

Instead of turngin off FPDMA AA on all NVIDIAs, implement
HFLAG_NO_FPDMA_AA, define additional board IDs and apply necessary
quirks.

This fixes bko#15481 and the list of quirks is verified by Peer Chen.

  http://bugzilla.kernel.org/show_bug.cgi?id=15481Signed-off-by: NTejun Heo <tj@kernel.org>
Cc: Peer Chen <pchen@nvidia.com>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

I've prepared a totally simple patch that, if I did it and measured it
correctly, reduces the text size as of the ppc-6xx-size command of
pata-mpc52xx by more than 10%, by reducing the rodata size from 0x4a4
to 0x17e bytes. This is simply done by changing the data types of the
ATA timing constants.

If you are interested at all, and it's worth the trouble, here the
details:

ppc-6xx-size:
     text data bss  dec  hex filename
old: 6532 1068   0 7600 1db0 pata-mpc52xx.o
new: 5718 1068   0 6786 1a82 pata-mpc52xx.o

The (assembler) code itself doesn't really change very much. I double
checked the final results inside mpc52xx-ata-apply-timings() and they
match. The driver is still working fine of course.
Signed-off-by: NRoman Fietze <roman.fietze@telemotive.de>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

ahci over time has grown a number of board IDs and it's a bit of mess
right now.  Clean it up such that,

* board_id_* now live in a separate enum board_ids and numbers are
  assigned automatically.

* Board IDs assigned to features are separated from the ones assigned
  to specific implementations and both are ordered alphabetically.

* For NV MCPs, define per-generation alias board_ids and assign
  matching aliases in the pci id table.  This makes mcp_linux, 67-73
  use board_ahci_mcp65 instead of board_ahci_yesncq.  Both are
  identical in content.

* Kill now unused board_ahci_nopmp and board_ahci_yesncq.

This patch doesn't cause any functional change but will make future
changes to board_ids and quirks much less painful.
Signed-off-by: NTejun Heo <tj@kernel.org>
Cc: Peer Chen <pchen@nvidia.com>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

According to section 10.3.1 of the AHCI spec, PxCMD.ST must not be set
unless there's a device attached. Following this saves us a measurable
quantity of power and does not impair hotplug support. Based on a patch
by Kristen Carlson Accardi.
Signed-off-by: NMatthew Garrett <mjg@redhat.com>
Cc: Kristen Carlson Accardi <kristen.c.accardi@intel.com>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

This can be used for AHCI-compatible interfaces implemented inside
System-On-Chip solutions, or AHCI devices connected via localbus.
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

This patch should contain no functional changes, just moves code
around.
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

Factor out some ahci_em_messages handling code from ahci_init_one().
We would like to reuse it for non-PCI devices.
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

Introduce ahci_pci_print_info() that now handles PCI stuff.
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

Move PCI stuff into ahci_pci_init_controller().
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

To make the function bus-independand we have to get rid of
"struct pci_dev *", so let's pass just "struct devce *".
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

Move PCI stuff into ahci_pci_reset_controller().
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

To make the function generic we have to get rid of "struct pci_dev *",
so let's pass just a "struct devce *".
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

Make ahci_save_initial_config() a bit more generic by introducing
force_port_map and mask_port_map arguments.

Move PCI stuff into ahci_pci_save_initial_config().
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

Currently the driver uses host->iomap to store all the iomapped BARs
of a PCI device (while AHCI devices actually use just a single memory
window).

We're going to teach AHCI to work with non-PCI buses, so there are two
options to make this work:

1. "fake" host->iomap array for non-PCI devices, and place the needed
   address at iomap[AHCI_PCI_BAR];
2. Get rid of host->iomap usage, instead introduce a private mmio
   field.

This patch implements the second option.
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

The imx CTS trigger level is left at its reset value that is 32
chars. Since the RX FIFO has 32 entries, when CTS is raised, the
FIFO already is full. However, some serial port devices first empty
their TX FIFO before stopping when CTS is raised, resulting in lost
chars.

This patch sets the trigger level lower so that other chars arrive
after CTS is raised, there is still room for 16 of them.

Signed-off-by: Valentin Longchamp<valentin.longchamp@epfl.ch>
Tested-by: Philippe Rétornaz<philippe.retornaz@epfl.ch>
Acked-by: Wolfram Sang<w.sang@pengutronix.de>
Cc: stable <stable@kernel.org>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>

Arnd noted:

After the "retry_open:" label, we first get the tty_mutex
and then the BKL. However a the end of tty_open, we jump
back to retry_open with the BKL still held. If we run into
this case, the tty_open function will be left with the BKL
still held.
Signed-off-by: NAlan Cox <alan@linux.intel.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Cc: stable <stable@kernel.org>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>

Commit 6acc6833
introduced NULL pointer dereference and kernel crash
on ppc32 machines while booting. Fix this bug now.
Reported-by: NLeonardo Chiquitto <leonardo.lists@gmail.com>
Tested-by: NLeonardo Chiquitto <leonardo.lists@gmail.com>
Signed-off-by: NAnatolij Gustschin <agust@denx.de>
Acked-by: NGrant Likely <grant.likely@secretlab.ca>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>

In certain circumstances, especially under heavy load, the AUXADC
completion interrupt may be detected after we've timed out waiting for
it.  That conversion would still succeed but the next conversion will
see the completion that was signalled by the interrupt for the previous
conversion and therefore not wait for the AUXADC conversion to run,
causing it to report failure.

Provide a simple, non-invasive cleanup by using try_wait_for_completion()
to ensure that the completion is not signalled before we wait.  Since
the AUXADC is run within a mutex we know there can only have been at
most one AUXADC interrupt outstanding.  A more involved change should
follow for the next merge window.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: NSamuel Ortiz <sameo@linux.intel.com>

With dma based spi transmission, data corruption is observed
occasionally. With dma buffers located right next to msg and
xfer fields, cache lines correctly flushed in preparation for
dma usage may be polluted again when writing to fields in the
same cache line.

Make sure cache fields used with dma do not share cache lines
with fields changed during dma handling. As both fields are part
of a struct that is allocated via kzalloc, thus cache aligned,
moving the fields to the 1st position and insert padding for
alignment does the job.
Signed-off-by: NOskar Schirmer <os@emlix.com>
Signed-off-by: NDaniel Glöckner <dg@emlix.com>
Signed-off-by: NOliver Schneidewind <osw@emlix.com>
Signed-off-by: NJohannes Weiner <jw@emlix.com>
Acked-by: NMike Frysinger <vapier@gentoo.org>
[dtor@mail.ru - changed to use ___cacheline_aligned as suggested
 by akpm]
Signed-off-by: NDmitry Torokhov <dtor@mail.ru>