1. 06 3月, 2019 1 次提交
  2. 05 3月, 2019 1 次提交
  3. 02 3月, 2019 1 次提交
    • C
      drm/i915: Use HW semaphores for inter-engine synchronisation on gen8+ · e8861964
      Chris Wilson 提交于
      Having introduced per-context seqno, we now have a means to identity
      progress across the system without feel of rollback as befell the
      global_seqno. That is we can program a MI_SEMAPHORE_WAIT operation in
      advance of submission safe in the knowledge that our target seqno and
      address is stable.
      
      However, since we are telling the GPU to busy-spin on the target address
      until it matches the signaling seqno, we only want to do so when we are
      sure that busy-spin will be completed quickly. To achieve this we only
      submit the request to HW once the signaler is itself executing (modulo
      preemption causing us to wait longer), and we only do so for default and
      above priority requests (so that idle priority tasks never themselves
      hog the GPU waiting for others).
      
      As might be reasonably expected, HW semaphores excel in inter-engine
      synchronisation microbenchmarks (where the 3x reduced latency / increased
      throughput more than offset the power cost of spinning on a second ring)
      and have significant improvement (can be up to ~10%, most see no change)
      for single clients that utilize multiple engines (typically media players
      and transcoders), without regressing multiple clients that can saturate
      the system or changing the power envelope dramatically.
      
      v3: Drop the older NEQ branch, now we pin the signaler's HWSP anyway.
      v4: Tell the world and include it as part of scheduler caps.
      
      Testcase: igt/gem_exec_whisper
      Testcase: igt/benchmarks/gem_wsim
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
      Reviewed-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20190301170901.8340-3-chris@chris-wilson.co.uk
      e8861964
  4. 21 2月, 2019 1 次提交
    • R
      drm/i915: MEI interface implementation · 9055aac7
      Ramalingam C 提交于
      Defining the mei-i915 interface functions and initialization of
      the interface.
      
      v2:
        Adjust to the new interface changes. [Tomas]
        Added further debug logs for the failures at MEI i/f.
        port in hdcp_port data is equipped to handle -ve values.
      v3:
        mei comp is matched for global i915 comp master. [Daniel]
        In hdcp_shim hdcp_protocol() is replaced with const variable. [Daniel]
        mei wrappers are adjusted as per the i/f change [Daniel]
      v4:
        port initialization is done only at hdcp2_init only [Danvet]
      v5:
        I915 registers a subcomponent to be matched with mei_hdcp [Daniel]
      v6:
        HDCP_disable for all connectors incase of comp_unbind.
        Tear down HDCP comp interface at i915_unload [Daniel]
      v7:
        Component init and fini are moved out of connector ops [Daniel]
        hdcp_disable is not called from unbind. [Daniel]
      v8:
        subcomponent name is dropped as it is already merged.
      Signed-off-by: NRamalingam C <ramalingam.c@intel.com>
      Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> [v11]
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      Link: https://patchwork.freedesktop.org/patch/msgid/1550338640-17470-5-git-send-email-ramalingam.c@intel.com
      9055aac7
  5. 08 2月, 2019 1 次提交
  6. 06 2月, 2019 1 次提交
  7. 29 1月, 2019 2 次提交
  8. 24 1月, 2019 1 次提交
  9. 17 1月, 2019 1 次提交
  10. 15 1月, 2019 2 次提交
  11. 09 1月, 2019 1 次提交
  12. 03 1月, 2019 1 次提交
  13. 02 1月, 2019 4 次提交
  14. 28 12月, 2018 1 次提交
  15. 13 12月, 2018 2 次提交
  16. 05 12月, 2018 1 次提交
    • T
      drm/i915: Record GT workarounds in a list · 00936779
      Tvrtko Ursulin 提交于
      To enable later verification of GT workaround state at various stages of
      driver lifetime, we record the list of applicable ones per platforms to a
      list, from which they are also applied.
      
      The added data structure is a simple array of register, mask and value
      items, which is allocated on demand as workarounds are added to the list.
      
      This is a temporary implementation which later in the series gets fused
      with the existing per context workaround list handling. It is separated at
      this stage since the following patch fixes a bug which needs to be as easy
      to backport as possible.
      
      Also, since in the following patch we will be adding a new class of
      workarounds (per engine) which can be applied from interrupt context, we
      straight away make the provision for safe read-modify-write cycle.
      
      v2:
       * Change dev_priv to i915 along the init path. (Chris Wilson)
       * API rename. (Chris Wilson)
      
      v3:
       * Remove explicit list size tracking in favour of growing the allocation
         in power of two chunks. (Chris Wilson)
      
      v4:
       Chris Wilson:
       * Change wa_list_finish to early return.
       * Copy workarounds using the compiler for static checking.
       * Do not bother zeroing unused entries.
       * Re-order struct i915_wa_list.
      
      v5:
       * kmalloc_array.
       * Whitespace cleanup.
      Signed-off-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com>
      Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
      Link: https://patchwork.freedesktop.org/patch/msgid/20181203133319.10174-1-tvrtko.ursulin@linux.intel.com
      (cherry picked from commit 25d140fa)
      Fixes: 59b449d5 ("drm/i915: Split out functions for different kinds of workarounds")
      Signed-off-by: NJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      00936779
  17. 04 12月, 2018 4 次提交
  18. 29 11月, 2018 1 次提交
  19. 09 11月, 2018 4 次提交
  20. 06 11月, 2018 1 次提交
  21. 02 11月, 2018 1 次提交
  22. 31 10月, 2018 1 次提交
  23. 30 10月, 2018 2 次提交
  24. 24 10月, 2018 1 次提交
  25. 12 10月, 2018 1 次提交
  26. 02 10月, 2018 1 次提交
  27. 27 9月, 2018 1 次提交