1. 17 11月, 2011 1 次提交
  2. 16 11月, 2011 1 次提交
  3. 01 11月, 2011 1 次提交
  4. 25 10月, 2011 3 次提交
  5. 20 10月, 2011 1 次提交
    • A
      phylib: Modify Vitesse RGMII skew settings · fddf86fc
      Andy Fleming 提交于
      The Vitesse driver was using the RGMII_ID interface type to determine if
      skew was necessary.  However, we want to move away from using that
      interface type, as it's really a property of the board's PHY connection.
      However, some boards depend on it, so we want to support it, while
      allowing new boards to use the more flexible "fixups" approach.  To do
      this, we extract the code which adds skew into its own function, and
      call that function when RGMII_ID has been selected.
      
      Another side-effect of this change is that if your PHY has skew set
      already, it doesn't clear it.  This way, the fixup code can modify the
      register without config_init then clearing it.
      Signed-off-by: NAndy Fleming <afleming@freescale.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      fddf86fc
  6. 19 10月, 2011 1 次提交
  7. 01 10月, 2011 2 次提交
  8. 29 9月, 2011 1 次提交
  9. 28 9月, 2011 1 次提交
  10. 27 9月, 2011 2 次提交
  11. 21 9月, 2011 1 次提交
  12. 27 8月, 2011 2 次提交
  13. 08 8月, 2011 1 次提交
  14. 27 7月, 2011 1 次提交
  15. 17 6月, 2011 4 次提交
  16. 24 5月, 2011 2 次提交
  17. 30 4月, 2011 2 次提交
  18. 31 3月, 2011 1 次提交
  19. 30 3月, 2011 1 次提交
    • M
      phylib: phy_attach_direct: phy_init_hw can fail, add cleanup · d005a09e
      Marc Kleine-Budde 提交于
      The function phy_attach_direct attaches the phy and calls phy_init_hw.
      phy_init_hw can fail, but the phy is still marked as attached. Successive
      calls to phy_attach_direct will fail because the phy is busy.
      
      [    1.020000] eth0: Freescale FEC PHY driver [Generic PHY] (mii_bus:phy_addr=1:00, irq=-1)
      [    1.030000] eth1: Freescale FEC PHY driver [Generic PHY] (mii_bus:phy_addr=1:01, irq=-1)
      [    2.050000] Sending DHCP requests .
      [    3.020000] PHY: 1:00 - Link is Up - 100/Full
      [    5.110000] ..... timed out!
      [   87.660000] IP-Config: Reopening network devices...
      [   88.190000] FEC: MDIO read timeout
      [   88.190000] eth0: could not attach to PHY
      [   88.190000] IP-Config: Failed to open eth0
      [   88.210000] FEC: MDIO read timeout
      [   88.210000] eth1: could not attach to PHY
      [   88.210000] IP-Config: Failed to open eth1
      [   88.220000] IP-Config: No network devices available.
      [   88.220000] Freeing init memory: 6968K
      
      [...]
      
      starting network interfaces...
      ip: RTNETLINK answers: File exists
      [   94.000000] net eth0: PHY already attached
      [   94.010000] eth0: could not attach to PHY
      ip: SIOCSIFFLAGS: Device or resource busy
      
      This patch adds phy_detach to clean up if phy_init_hw fails.
      Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      d005a09e
  20. 15 3月, 2011 1 次提交
  21. 01 3月, 2011 1 次提交
  22. 15 2月, 2011 1 次提交
  23. 12 2月, 2011 1 次提交
  24. 11 12月, 2010 1 次提交
  25. 29 11月, 2010 1 次提交
  26. 23 11月, 2010 3 次提交
    • D
      of/phylib: Use device tree properties to initialize Marvell PHYs. · cf41a51d
      David Daney 提交于
      Some aspects of PHY initialization are board dependent, things like
      indicator LED connections and some clocking modes cannot be determined
      by probing.  The dev_flags element of struct phy_device can be used to
      control these things if an appropriate value can be passed from the
      Ethernet driver.  We run into problems however if the PHY connections
      are specified by the device tree.  There is no way for the Ethernet
      driver to know what flags it should pass.
      
      If we are using the device tree, the struct phy_device will be
      populated with the device tree node corresponding to the PHY, and we
      can extract extra configuration information from there.
      
      The next question is what should the format of that information be?
      It is highly device specific, and the device tree representation
      should not be tied to any arbitrary kernel defined constants.  A
      straight forward representation is just to specify the exact bits that
      should be set using the "marvell,reg-init" property:
      
            phy5: ethernet-phy@5 {
              reg = <5>;
              compatible = "marvell,88e1149r";
              marvell,reg-init =
                      /* led[0]:1000, led[1]:100, led[2]:10, led[3]:tx */
                      <3 0x10 0 0x5777>, /* Reg 3,16 <- 0x5777 */
                      /* mix %:0, led[0123]:drive low off hiZ */
                      <3 0x11 0 0x00aa>, /* Reg 3,17 <- 0x00aa */
                      /* default blink periods. */
                      <3 0x12 0 0x4105>, /* Reg 3,18 <- 0x4105 */
                      /* led[4]:rx, led[5]:dplx, led[45]:drive low off hiZ */
                      <3 0x13 0 0x0a60>; /* Reg 3,19 <- 0x0a60 */
            };
      
            phy6: ethernet-phy@6 {
              reg = <6>;
              compatible = "marvell,88e1118";
              marvell,reg-init =
                      /* Fix rx and tx clock transition timing */
                      <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
                      /* Adjust LED drive. */
                      <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
                      /* irq, blink-activity, blink-link */
                      <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
            };
      
      The Marvell PHYs have a page select register at register 22 (0x16), we
      can specify any register by its page and register number.  These are
      the first and second word.  The third word contains a mask to be ANDed
      with the existing register value, and the fourth word is ORed with the
      result to yield the new register value.  The new marvell_of_reg_init
      function leaves the page select register unchanged, so a call to it
      can be dropped into the .config_init functions without unduly
      affecting the state of the PHY.
      
      If CONFIG_OF_MDIO is not set, there is no of_node, or no
      "marvell,reg-init" property, the PHY initialization is unchanged.
      Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
      Cc: Grant Likely <grant.likely@secretlab.ca>
      Cc: Cyril Chemparathy <cyril@ti.com>
      Cc: David Daney <ddaney@caviumnetworks.com>
      Cc: Arnaud Patard <arnaud.patard@rtp-net.org>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Reviewed-by: NGrant Likely <grant.likely@secretlab.ca>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      cf41a51d
    • D
      phylib: Add support for Marvell 88E1149R devices. · 90600732
      David Daney 提交于
      The 88E1149R is 10/100/1000 quad-gigabit Ethernet PHY.  The
      .config_aneg function can be shared with 88E1118, but it needs its own
      .config_init.
      Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
      Cc: Cyril Chemparathy <cyril@ti.com>
      Cc: Arnaud Patard <arnaud.patard@rtp-net.org>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Wolfram Sang <w.sang@pengutronix.de>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      90600732
    • D
      phylib: Use common page register definition for Marvell PHYs. · 27d916d6
      David Daney 提交于
      The definition of the Marvell PHY page register is not specific to
      88E1121, so rename the macro to MII_MARVELL_PHY_PAGE, and use it
      throughout.
      Suggested-by: NCyril Chemparathy <cyril@ti.com>
      Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
      Cc: Cyril Chemparathy <cyril@ti.com>
      Cc: Arnaud Patard <arnaud.patard@rtp-net.org>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      27d916d6
  27. 30 10月, 2010 1 次提交
  28. 25 10月, 2010 1 次提交