When using MCLK is configured for 19.2 Mhz, clock slicer should be
enabled and HPPLL should be bypassed in clock path.
Signed-off-by: NJorge Eduardo Candelaria <jorge.candelaria@ti.com>
Signed-off-by: NMargarita Olaya Cabrera <magi.olaya@ti.com>
Acked-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: NLiam Girdwood <lrg@slimlogic.co.uk>

Add control to enable earphone driver in TWL6040 codec. This driver
is connected to HSDAC Left.
Signed-off-by: NJorge Eduardo Candelaria <jorge.candelaria@ti.com>
Signed-off-by: NMargarita Olaya Cabrera <magi.olaya@ti.com>
Acked-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: NLiam Girdwood <lrg@slimlogic.co.uk>

The core will ensure that the device is in either STANDBY or OFF bias
before suspending, restoring the bias in the driver is unneeded. Some
drivers doing slightly more roundabout things have been left alone
for now.
Tested-by: NPeter Ujfalusi <peter.ujfalusi@nokia.com>
Acked-by: NLiam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

Conversions to snd_soc_codec_{get|set}_drvdata() were missing in some files
in the previous commit.
Signed-off-by: NTakashi Iwai <tiwai@suse.de>

Signed-off-by: NTakashi Iwai <tiwai@suse.de>

Signed-off-by: NStephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: NTakashi Iwai <tiwai@suse.de>

Initial version of TWL6040 codec driver.

The TWL6040 codec uses a proprietary PDM-based digital audio interface.
Audio paths supported are:

- Input: Main Mic, Sub Mic, Headset Mic, Auxiliary-FM Left/Right
- Output: Headset Left/Right, Handsfree Left/Right

TWL6040 codec supports power-up/down manual and automatic sequence.
Manual sequence is done through a specific register writes sequence.
Automatic sequence is done when the codec is powered-up through the
external AUDPWRON line. The completion of the sequence is signaled
through the audio interrupt.

TWL6040 codec sysclk can be provided by: low-power or high
performance PLL:

- The low-power PLL takes a low-frequency input at 32,768 Hz and
generates an approximate of 17.64 or 19.2 MHz (for 44.1 KHz and 48 KHz
respectively)

- The high-performance PLL generates an exact 19.2 MHz clock signal
from high-frequency input at 12/19.2/26/38.4 MHz.

Low-power playback mode is a special scenario where only headset path
(headset DAC and driver) is active.

For the particular case of headset path, PLL being used defines the
headset power mode: low-power, high-performance.
Signed-off-by: NMisael Lopez Cruz <x0052729@ti.com>
Signed-off-by: NJorge Eduardo Candelaria <jorge.candelaria@ti.com>
Signed-off-by: NMargarita Olaya Cabrera <magi.olaya@ti.com>
Acked-by: NLiam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>