1. 25 10月, 2016 10 次提交
    • S
      drm/i915: Support for GuC interrupts · 26705e20
      Sagar Arun Kamble 提交于
      There are certain types of interrupts which Host can receive from GuC.
      GuC ukernel sends an interrupt to Host for certain events, like for
      example retrieve/consume the logs generated by ukernel.
      This patch adds support to receive interrupts from GuC but currently
      enables & partially handles only the interrupt sent by GuC ukernel.
      Future patches will add support for handling other interrupt types.
      
      v2:
      - Use common low level routines for PM IER/IIR programming (Chris)
      - Rename interrupt functions to gen9_xxx from gen8_xxx (Chris)
      - Replace disabling of wake ref asserts with rpm get/put (Chris)
      
      v3:
      - Update comments for more clarity. (Tvrtko)
      - Remove the masking of GuC interrupt, which was kept masked till the
        start of bottom half, its not really needed as there is only a
        single instance of work item & wq is ordered. (Tvrtko)
      
      v4:
      - Rebase.
      - Rename guc_events to pm_guc_events so as to be indicative of the
        register/control block it is associated with. (Chris)
      - Add handling for back to back log buffer flush interrupts.
      
      v5:
      - Move the read & clearing of register, containing Guc2Host message
        bits, outside the irq spinlock. (Tvrtko)
      
      v6:
      - Move the log buffer flush interrupt related stuff to the following
        patch so as to do only generic bits in this patch. (Tvrtko)
      - Rebase.
      
      v7:
      - Remove the interrupts_enabled check from gen9_guc_irq_handler, want to
        process that last interrupt also before disabling the interrupt, sync
        against the work queued by irq handler will be done by caller disabling
        the interrupt.
      Signed-off-by: NSagar Arun Kamble <sagar.a.kamble@intel.com>
      Signed-off-by: NAkash Goel <akash.goel@intel.com>
      Reviewed-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com>
      Signed-off-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com>
      26705e20
    • A
      drm/i915: Add low level set of routines for programming PM IER/IIR/IMR register set · f4e9af4f
      Akash Goel 提交于
      So far PM IER/IIR/IMR registers were being used only for Turbo related
      interrupts. But interrupts coming from GuC also use the same set.
      As a precursor to supporting GuC interrupts, added new low level routines
      so as to allow sharing the programming of PM IER/IIR/IMR registers between
      Turbo & GuC.
      Also similar to PM IMR, maintaining a bitmask for PM IER register, to allow
      easy sharing of it between Turbo & GuC without involving a rmw operation.
      
      v2:
      - For appropriateness & avoid any ambiguity, rename old functions
        enable/disable pm_irq to mask/unmask pm_irq and rename new functions
        enable/disable pm_interrupts to enable/disable pm_irq. (Tvrtko)
      - Use u32 in place of uint32_t. (Tvrtko)
      
      v3:
      - Rename the fields pm_irq_mask & pm_ier_mask and do some cleanup. (Chris)
      - Rebase.
      
      v4: Fix the inadvertent disabling of User interrupt for VECS ring causing
          failure for certain IGTs.
      
      v5: Use dev_priv with HAS_VEBOX macro. (Tvrtko)
      Suggested-by: NChris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: NAkash Goel <akash.goel@intel.com>
      Reviewed-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com>
      Signed-off-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com>
      f4e9af4f
    • A
      drm/i915: New structure to contain GuC logging related fields · d6b40b4b
      Akash Goel 提交于
      So far there were 2 fields related to GuC logs in 'intel_guc' structure.
      For the support of capturing GuC logs & storing them in a local buffer,
      multiple new fields would have to be added. This warrants a separate
      structure to contain the fields related to GuC logging state.
      Added a new structure 'intel_guc_log' and instance of it inside
      'intel_guc' structure.
      
      v2: Rebase.
      Signed-off-by: NAkash Goel <akash.goel@intel.com>
      Reviewed-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com>
      Signed-off-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com>
      d6b40b4b
    • S
      drm/i915: Add GuC ukernel logging related fields to fw interface file · 5d34e85a
      Sagar Arun Kamble 提交于
      The first page of the GuC log buffer contains state info or meta data
      which is required to parse the logs contained in the subsequent pages.
      The structure representing the state info is added to interface file
      as Driver would need to handle log buffer flush interrupts from GuC.
      Added an enum for the different message/event types that can be send
      by the GuC ukernel to Host.
      Also added 2 new Host to GuC action types to inform GuC when Host has
      flushed the log buffer and forcefuly cause the GuC to send a new
      log buffer flush interrupt.
      
      v2:
      - Make documentation of log buffer state structure more elaborate &
        rename LOGBUFFERFLUSH action to LOG_BUFFER_FLUSH for consistency.(Tvrtko)
      
      v3: Add GuC log buffer layout diagram for more clarity.
      Signed-off-by: NSagar Arun Kamble <sagar.a.kamble@intel.com>
      Signed-off-by: NAkash Goel <akash.goel@intel.com>
      Reviewed-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com>
      Signed-off-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com>
      5d34e85a
    • S
      drm/i915: Decouple GuC log setup from verbosity parameter · b1e37103
      Sagar Arun Kamble 提交于
      GuC Log buffer allocation was tied up with verbosity level module param
      i915.guc_log_level. User would be given a provision to enable firmware
      logging at runtime, through a host2guc action, and not necessarily during
      Driver load time. But the address of log buffer can be passed only in
      init params, at firmware load time, so GuC has to be reset and firmware
      needs to be reloaded to pass the log buffer address at runtime.
      To avoid reset of GuC & reload of firmware, allocation of log buffer will
      be done always but logging would be enabled initially on GuC side based on
      the value of module parameter guc_log_level.
      
      v2: Update commit message to describe the constraint with allocation of
          log buffer at runtime. (Tvrtko)
      
      v3: Rebase.
      Signed-off-by: NSagar Arun Kamble <sagar.a.kamble@intel.com>
      Signed-off-by: NAkash Goel <akash.goel@intel.com>
      Reviewed-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com>
      Signed-off-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com>
      b1e37103
    • D
      Merge remote-tracking branch 'airlied/drm-next' into drm-intel-next-queued · f9bf1d97
      Daniel Vetter 提交于
      Backmerge because Chris Wilson needs the very latest&greates of
      Gustavo Padovan's sync_file work, specifically the refcounting changes
      from:
      
      commit 30cd85dd
      Author: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
      Date:   Wed Oct 19 15:48:32 2016 -0200
      
          dma-buf/sync_file: hold reference to fence when creating sync_file
      
      Also good to sync in general since git tends to get confused with the
      cherry-picking going on.
      Signed-off-by: NDaniel Vetter <daniel.vetter@intel.com>
      f9bf1d97
    • D
      Merge tag 'drm-intel-next-2016-10-24' of git://anongit.freedesktop.org/drm-intel into drm-next · 5481e27f
      Dave Airlie 提交于
      - first slice of the gvt device model (Zhenyu et al)
      - compression support for gpu error states (Chris)
      - sunset clause on gpu errors resulting in dmesg noise telling users
        how to report them
      - .rodata diet from Tvrtko
      - switch over lots of macros to only take dev_priv (Tvrtko)
      - underrun suppression for dp link training (Ville)
      - lspcon (hmdi 2.0 on skl/bxt) support from Shashank Sharma, polish
        from Jani
      - gen9 wm fixes from Paulo&Lyude
      - updated ddi programming for kbl (Rodrigo)
      - respect alternate aux/ddc pins (from vbt) for all ddi ports (Ville)
      
      * tag 'drm-intel-next-2016-10-24' of git://anongit.freedesktop.org/drm-intel: (227 commits)
        drm/i915: Update DRIVER_DATE to 20161024
        drm/i915: Stop setting SNB min-freq-table 0 on powersave setup
        drm/i915/dp: add lane_count check in intel_dp_check_link_status
        drm/i915: Fix whitespace issues
        drm/i915: Clean up DDI DDC/AUX CH sanitation
        drm/i915: Respect alternate_ddc_pin for all DDI ports
        drm/i915: Respect alternate_aux_channel for all DDI ports
        drm/i915/gen9: Remove WaEnableYV12BugFixInHalfSliceChicken7
        drm/i915: KBL - Recommended buffer translation programming for DisplayPort
        drm/i915: Move down skl/kbl ddi iboost and n_edp_entires fixup
        drm/i915: Add a sunset clause to GPU hang logging
        drm/i915: Stop reporting error details in dmesg as well as the error-state
        drm/i915/gvt: do not ignore return value of create_scratch_page
        drm/i915/gvt: fix spare warnings on odd constant _Bool cast
        drm/i915/gvt: mark symbols static where possible
        drm/i915/gvt: fix sparse warnings on different address spaces
        drm/i915/gvt: properly access enabled intel_engine_cs
        drm/i915/gvt: Remove defunct vmap_batch()
        drm/i915/gvt: Use common mapping routines for shadow_bb object
        drm/i915/gvt: Use common mapping routines for indirect_ctx object
        ...
      5481e27f
    • D
      Merge tag 'topic/drm-misc-2016-10-24' of git://anongit.freedesktop.org/drm-intel into drm-next · 61d0a04d
      Dave Airlie 提交于
      First -misc pull for 4.10:
      - drm_format rework from Laurent
      - reservation patches from Chris that missed 4.9.
      - aspect ratio support in infoframe helpers and drm mode/edid code
        (Shashank Sharma)
      - rotation rework from Ville (first parts at least)
      - another attempt at the CRC debugfs interface from Tomeu
      - piles and piles of misc patches all over
      
      * tag 'topic/drm-misc-2016-10-24' of git://anongit.freedesktop.org/drm-intel: (55 commits)
        drm: Use u64 for intermediate dotclock calculations
        drm/i915: Use the per-plane rotation property
        drm/omap: Use per-plane rotation property
        drm/omap: Set rotation property initial value to BIT(DRM_ROTATE_0) insted of 0
        drm/atmel-hlcdc: Use per-plane rotation property
        drm/arm: Use per-plane rotation property
        drm: Add support for optional per-plane rotation property
        drm/atomic: Reject attempts to use multiple rotation angles at once
        drm: Add drm_rotation_90_or_270()
        dma-buf/sync_file: hold reference to fence when creating sync_file
        drm/virtio: kconfig: Fixup white space.
        drm/fence: release fence reference when canceling event
        drm/i915: Handle early failure during intel_get_load_detect_pipe
        drm/fb_cma_helper: do not free fbdev if there is none
        drm: fix sparse warnings on undeclared symbols in crc debugfs
        gpu: Remove depends on RESET_CONTROLLER when not a provider
        i915: don't call drm_atomic_state_put on invalid pointer
        drm: Don't export the drm_fb_get_bpp_depth() function
        drm/arm: mali-dp: Replace drm_fb_get_bpp_depth() with drm_format_plane_cpp()
        drm: vmwgfx: Replace drm_fb_get_bpp_depth() with drm_format_info()
        ...
      61d0a04d
    • P
      drm/i915/fbc: fix FBC_COMPRESSION_MASK on BDW+ · 0fc6a9dc
      Paulo Zanoni 提交于
      Its size is 11:0 instead of 10:0. Found by inspecting the spec. I'm
      not aware of any real-world IGT failures caused by this.
      Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com>
      Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1477065346-13736-2-git-send-email-paulo.r.zanoni@intel.com
      0fc6a9dc
    • P
      drm/i915/fbc: fix CFB size calculation for gen8+ · 79f2624b
      Paulo Zanoni 提交于
      Broadwell and newer actually compress up to 2560 lines instead of 2048
      (as documented in the FBC_CTL page). If we don't take this into
      consideration we end up reserving too little stolen memory for the
      CFB, so we may allocate something else (such as a ring) right after
      what we reserved, and the hardware will overwrite it with the contents
      of the CFB when FBC is active, causing GPU hangs. Another possibility
      is that the CFB may be allocated at the very end of the available
      space, so the CFB will overlap the reserved stolen area, leading to
      FIFO underruns.
      
      This bug has always been a problem on BDW (the only affected platform
      where FBC is enabled by default), but it's much easier to reproduce
      since the following commit:
          commit c58b735f
          Author: Chris Wilson <chris@chris-wilson.co.uk>
          Date:   Thu Aug 18 17:16:57 2016 +0100
              drm/i915: Allocate rings from stolen
      
      Of course, you can only reproduce the bug if your screen is taller
      than 2048 lines.
      
      Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98213
      Fixes: a98ee793 ("drm/i915/fbc: enable FBC by default on HSW and BDW")
      Cc: <stable@vger.kernel.org> # v4.6+
      Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com>
      Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1477065346-13736-1-git-send-email-paulo.r.zanoni@intel.com
      79f2624b
  2. 24 10月, 2016 14 次提交
  3. 23 10月, 2016 5 次提交
  4. 22 10月, 2016 11 次提交