- 30 8月, 2022 12 次提交
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由 YuBiao Wang 提交于
[Why] In amdgpu_cs_ioctl, amdgpu_job_free could be performed ealier if there is -ERESTARTSYS error. In this case, job->hw_fence could be not initialized yet. Putting hw_fence during amdgpu_job_free could lead to a use-after-free warning. [How] Check if drm_sched_job_init is performed before job_free by checking s_fence. v2: Check hw_fence.ops instead since it could be NULL if fence is not initialized. Reverse the condition since !=NULL check is discouraged in kernel. Signed-off-by: NYuBiao Wang <YuBiao.Wang@amd.com> Reviewed-by: NAndrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Duncan Ma 提交于
[Why] When ODM is enabled, H timing control register reset to 0. Div mode manual field get overwritten causing no display on certain modes for dcn314. [How] Use REG_UPDATE instead of REG_SET to set div_mode field. Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com> Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: NBrian Chang <Brian.Chang@amd.com> Signed-off-by: NDuncan Ma <duncan.ma@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Lewis Huang 提交于
[Why] LTTPR caps will read fail if aux channel is not active. [How] 1.Perform 600 read upto 10 retry with 1ms delay in between. 2.If fail, return false and trigger another retry detection. 3.If pass, read LTTPR caps in retrieve link caps. Reviewed-by: NJimmy Kizito <Jimmy.Kizito@amd.com> Acked-by: NBrian Chang <Brian.Chang@amd.com> Signed-off-by: NLewis Huang <Lewis.Huang@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 George Shen 提交于
[Why] Each index in the DPSTREAMCLK_CNTL register phyiscally maps 1-to-1 with HPO stream encoder instance. On the other hand, each index in DTBCLK_P_CNTL physically maps 1-to-1 with OTG instance. Current DCN32 DPSTREAMCLK_CLK programing assumes that OTG instance always maps 1-to-1 with HPO stream encoder instance. This is not always guaranteed and can result in blackscreen. [How] Program the correct dpstreamclk instance with the correct dtbclk_p source. Reviewed-by: NAriel Bernstein <Eric.Bernstein@amd.com> Acked-by: NBrian Chang <Brian.Chang@amd.com> Signed-off-by: NGeorge Shen <george.shen@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Alvin Lee 提交于
[Description] There can be SubVP scheduling issues if a SubVP display is chosen has ActiveDramClockChangeLatency > 0. Block this case for now, and enable Vactive case (later) to handle this. Reviewed-by: NJun Lei <Jun.Lei@amd.com> Acked-by: NBrian Chang <Brian.Chang@amd.com> Signed-off-by: NAlvin Lee <Alvin.Lee2@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Taimur Hassan 提交于
[Why & How] Add addtional check in CalculateODMMode for cases where the ODM combine is needed due to number of DSC slices. Reviewed-by: NAlvin Lee <alvin.lee2@amd.com> Acked-by: NBrian Chang <Brian.Chang@amd.com> Signed-off-by: NTaimur Hassan <Syed.Hassan@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Aric Cyr 提交于
This version brings along following fixes: - Modify pipe split policy - Fix odm 2:1 policy in 4k144 mode - Correct HDMI ODM combine policy - Change AUX NACK behavior - Change runtime initialization for DCN32/321 - Fix cursor flicker in PSRSU - Fix k1/k2 divider for virtual signal for DCN32 - Free phantom plane after removing the context - Add interface to track PHY state - Add SubVP scaling case - Add log clock table for SMU - Fix atomic_check check - Fix SMU 13.0.0 driver_if header - Fix doorbells allocation Acked-by: NBrian Chang <Brian.Chang@amd.com> Signed-off-by: NAric Cyr <aric.cyr@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Yang Yingliang 提交于
Add missing pci_disable_device() if amdgpu_device_resume() fails. Fixes: 8e4d5d43 ("drm/amdgpu: Handling of amdgpu_device_resume return value for graceful teardown") Signed-off-by: NYang Yingliang <yangyingliang@huawei.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 sunliming 提交于
Fixes the following smatch warning: drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dmub_srv.c:311 dc_dmub_srv_p_state_delegate() warn: variable dereferenced before check 'dc' (see line 309) Reported-by: Nkernel test robot <lkp@intel.com> Reported-by: NDan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Nsunliming <sunliming@kylinos.cn> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 ye xingchen 提交于
Return the value sdma_v5_2_start() directly instead of storing it in another redundant variable. Reported-by: NZeal Robot <zealci@zte.com.cn> Signed-off-by: Nye xingchen <ye.xingchen@zte.com.cn> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Graham Sider 提交于
New GFX11 MES FW adds the trap_en bit. For now hardcode to 1 (traps enabled). Signed-off-by: NGraham Sider <Graham.Sider@amd.com> Acked-by: NFelix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: NHarish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Guchun Chen 提交于
Below driver load error will be printed, not friendly to end user. amdgpu: ATOM BIOS: 113-D603GLXE-077 [drm] FRU: Failed to get size field [drm:amdgpu_fru_get_product_info [amdgpu]] *ERROR* Failed to read FRU Manufacturer, ret:-5 Signed-off-by: NGuchun Chen <guchun.chen@amd.com> Reviewed-by: NKent Russell <kent.russell@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 26 8月, 2022 28 次提交
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由 Bernard Zhao 提交于
This patch fix cocci warning: drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c:1816:6-8: WARNING: possible condition with no effect (if == else). Signed-off-by: NBernard Zhao <bernard@vivo.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Bernard Zhao 提交于
This patch fix cocci warning: drivers/gpu/drm/amd/display/dc/core/dc.c:3335:2-4: WARNING: possible condition with no effect (if == else). Signed-off-by: NBernard Zhao <bernard@vivo.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Bernard Zhao 提交于
This patch fix potential memory leak (clk_src) when function run into last return NULL. Signed-off-by: NBernard Zhao <bernard@vivo.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Bernard Zhao 提交于
This patch fix potential memory leak (clk_src) when function run into last return NULL. s/free/kfree/ - Alex Signed-off-by: NBernard Zhao <bernard@vivo.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Qu Huang 提交于
The mmVM_L2_CNTL3 register is not assigned an initial value Signed-off-by: NQu Huang <jinsdb@126.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Rafael J. Wysocki 提交于
According to the ACPI specification [1], the ACPI_FADT_LOW_POWER_S0 flag merely means that it is better to use low-power S0 idle on the given platform than S3 (provided that the latter is supported) and it doesn't preclude using either of them (which of them will be used depends on the choices made by user space). However, on some systems that flag is used to indicate whether or not to enable special firmware mechanics allowing the system to save more energy when suspended to idle. If that flag is unset, doing so is generally risky. Accordingly, add a comment to explain the ACPI_FADT_LOW_POWER_S0 check in amdgpu_acpi_is_s0ix_active(), the purpose of which is otherwise somewhat unclear. Link: https://uefi.org/specs/ACPI/6.4/05_ACPI_Software_Programming_Model/ACPI_Software_Programming_Model.html#fixed-acpi-description-table-fadt # [1] Reviewed-by: NMario Limonciello <mario.limonciello@amd.com> Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Yu Zhe 提交于
time_after() deals with timer wrapping correctly. Signed-off-by: NYu Zhe <yuzhe@nfschina.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Guchun Chen 提交于
'free PSP TMR buffer' happens in suspend, but sometimes in mGPU config, it mixes with PSP resume log printing from another GPU, which is confusing. So use dev_info instead of DRM_INFO for printing. [drm] PSP is resuming... [drm] reserve 0xa00000 from 0x877e000000 for PSP TMR amdgpu 0000:e3:00.0: amdgpu: GECC is enabled amdgpu 0000:e3:00.0: amdgpu: SECUREDISPLAY: securedisplay ta ucode is not available amdgpu 0000:e3:00.0: amdgpu: SMU is resuming... amdgpu 0000:e3:00.0: amdgpu: smu driver if version = 0x00000040, smu fw if version = 0x00000041, smu fw program = 0, version = 0x003a5400 (58.84.0) amdgpu 0000:e3:00.0: amdgpu: SMU driver if version not matched amdgpu 0000:e3:00.0: amdgpu: dpm has been enabled amdgpu 0000:e3:00.0: amdgpu: SMU is resumed successfully! [drm] DMUB hardware initialized: version=0x02020014 [drm] free PSP TMR buffer [drm] kiq ring mec 2 pipe 1 q 0 Signed-off-by: NGuchun Chen <guchun.chen@amd.com> Reviewed-by: NEvan Quan <evan.quan@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Guchun Chen 提交于
adev_to_drm is used everywhere in amdgpu code, so modify it to keep consistency. Signed-off-by: NGuchun Chen <guchun.chen@amd.com> Reviewed-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Likun Gao 提交于
Enable GFX11 MGCG perfmon setting. V2: set rlc to saft mode before setting. Signed-off-by: NLikun Gao <Likun.Gao@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Chengming Gui 提交于
Avoid soft reset, even ip hang check (ring/ib test) when gpu recovery disabled. v2: add missing "}" Signed-off-by: NChengming Gui <Jack.Gui@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Prike Liang 提交于
Correct the isa version for handling KFD test. Fixes: 7c4f4f19 ("drm/amdkfd: Add GC 10.3.6 and 10.3.7 KFD definitions") Signed-off-by: NPrike Liang <Prike.Liang@amd.com> Reviewed-by: NAaron Liu <aaron.liu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Mukul Joshi 提交于
When translate_further is enabled, page table depth needs to be updated. This was missing on Arcturus MMHUB init. This was causing address translations to fail for SDMA user-mode queues. Fixes: 352e683b ("drm/amdgpu: Enable translate_further to extend UTCL2 reach") Reviewed-by: NFelix Kuehling <Felix.Kuehling@amd.com> Acked-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NMukul Joshi <mukul.joshi@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Felix Kuehling 提交于
Only allocate doorbells when the first queue is created on a GPU or the doorbells need to be mapped into CPU or GPU virtual address space. This avoids allocating doorbells unnecessarily and can allow more processes to use KFD on multi-GPU systems. Signed-off-by: NFelix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: NKent Russell <kent.Russell@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Evan Quan 提交于
To fit the latest 78.53 PMFW. Signed-off-by: NEvan Quan <evan.quan@amd.com> Reviewed-by: NFeifei Xu <Feifei.Xu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Roman Li 提交于
[Why] We have 2 back-to-back checks for skipping connectors. Logically one of them will do the job. [How] Remove redundant check. Reviewed-by: NHersen Wu <hersenxs.wu@amd.com>> Acked-by: NBrian Chang <Brian.Chang@amd.com> Signed-off-by: NRoman Li <roman.li@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Leo Chen 提交于
[Why & How] Adding log for clock table from SMU helps with the debugging process. Implemented using DC_LOG_SMU to output log. Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com> Acked-by: NBrian Chang <Brian.Chang@amd.com> Signed-off-by: NLeo Chen <sancchen@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Alvin Lee 提交于
[Description] Uncomment scaling cmd assignment since FW headers are now promoted. Reviewed-by: NMartin Leung <Martin.Leung@amd.com> Acked-by: NBrian Chang <Brian.Chang@amd.com> Signed-off-by: NAlvin Lee <Alvin.Lee2@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Alvin Lee 提交于
[Why] Sometimes pixel clock needs to remain active after transmitter disable. [How] Use update_phy_state to track PHY state after stream enable/disable and program pixel clock as needed. Reviewed-by: NAlvin Lee <alvin.lee2@amd.com> Acked-by: NBrian Chang <Brian.Chang@amd.com> Signed-off-by: NTaimur Hassan <Syed.Hassan@amd.com> Signed-off-by: NAlvin Lee <alvin.lee2@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Alvin Lee 提交于
[Description] Refcount is incremented on allocation and when adding to the context. Therefore we must release the phantom plane and stream after removing from the context. Reviewed-by: NAric Cyr <Aric.Cyr@amd.com> Acked-by: NBrian Chang <Brian.Chang@amd.com> Signed-off-by: NAlvin Lee <Alvin.Lee2@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Aurabindo Pillai 提交于
[Why&How] When using IGT, kms_bw multi display tests trigger an assert since we ignore virtual signal type. k1/k2 dividers should be correctly programmed if VSYNC needs to be correct. Add the appropriate condition to the if arm to fix this. Reviewed-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: NBrian Chang <Brian.Chang@amd.com> Signed-off-by: NAurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Robin Chen 提交于
[Why] The DAL driver may transmit the wrong cursor position to PSRSU DMUB driver when there are multiple planes. [How] Currently the driver apply the HW cursor on the top plane. So we should only transmit the cursor position on the top plane to PSRSU DMUB driver. Reviewed-by: NAnthony Koo <Anthony.Koo@amd.com> Acked-by: NBrian Chang <Brian.Chang@amd.com> Signed-off-by: NRobin Chen <po-tchen@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Aurabindo Pillai 提交于
DC was using compile time initialization of register addresses using SR_* macros and their variants. These have been converted to use runtime initialization. The REG_STRUCT macro is a definition that is added to SR_* macros. During initialization, this must be defined before SR_* macros are invoked, which are in turn invoked through various IP initialization macros. Reviewed-by: NHarry Wentland <Harry.Wentland@amd.com> Acked-by: NBrian Chang <Brian.Chang@amd.com> Signed-off-by: NAurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Aurabindo Pillai 提交于
DC was using compile time initialization of register addresses using SR_* macros and their variants. These have been converted to use runtime initialization. The REG_STRUCT macro is a definition that is added to SR_* macros. During initialization, this must be defined before SR_* macros are invoked, which are in turn invoked through various IP initialization macros. Reviewed-by: NHarry Wentland <Harry.Wentland@amd.com> Acked-by: NBrian Chang <Brian.Chang@amd.com> Signed-off-by: NAurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Ilya Bakoulin 提交于
[Why] Retrying on receiving a NACK can result in long overall EDID read times in some cases. [How] Retry only on DEFER and return immediately on NACK. Reviewed-by: NAric Cyr <Aric.Cyr@amd.com> Acked-by: NBrian Chang <Brian.Chang@amd.com> Signed-off-by: NIlya Bakoulin <Ilya.Bakoulin@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Saaem Rizvi 提交于
[WHY] Reprogramming the stream despite no changes in ODM combine mode. Reprogramming the stream would cause intermittent black screen on display which could only be recovered through enable/disable sequence. [HOW] Fixed bug where we detected a change in ODM combine mode despite ODM combine mode being disabled. Also removed code which required stream to be reprogrammed once a change in ODM combine mode was noticed. Lastly we do not support dynamic ODM switching for HDMI TMDS and FRL on DCN32, therefore we never want to change its ODM policy. Reviewed-by: NSamson Tam <Samson.Tam@amd.com> Acked-by: NBrian Chang <Brian.Chang@amd.com> Signed-off-by: NSaaem Rizvi <SyedSaaem.Rizvi@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Samson Tam 提交于
[Why] odm 2:1 policy is splitting the pipes in 4k144. then in subvp code, we merge the pipes. but since the configuration is unsupported, we keep the pipes split [How] for unsupported subvp configuration, redo the dml and pipe split calls Reviewed-by: NAlvin Lee <alvin.lee2@amd.com> Reviewed-by: NJun Lei <Jun.Lei@amd.com> Acked-by: NBrian Chang <Brian.Chang@amd.com> Signed-off-by: NSamson Tam <samson.tam@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Derek Lai 提交于
[Why] RV2 do not change pipe split policy in the minimal pipe split transition state. This will unblock mode support on some parts that limit to DPM0 for power reason. [How] Do not change pipe split policy in the minimal pipe split transition state to allow 4k multi display configs to be supported at DPM0. Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com> Acked-by: NBrian Chang <Brian.Chang@amd.com> Signed-off-by: NDerek Lai <Derek.Lai@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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