1. 20 12月, 2007 1 次提交
    • M
      [POWERPC] Push down or eliminate smp_processor_id calls in xics code · d7cf0edb
      Milton Miller 提交于
      The per-processor interrupt request register and current processor
      priority register are only accessed on the current cpu.  In fact the
      hypervisor doesn't even let us choose which cpu's registers to access.
      
      The only function to use cpu twice is xics_migrate_irqs_away, not a fast
      path.  But we can cache the result of get_hard_processor_id() instead of
      calling get_hard_smp_processor_id(cpu) in a loop across the call to rtas.
      
      Years ago the irq code passed smp_processor_id into get_irq, I thought
      we might initialize the CPPR third party at boot as an extra measure of
      saftey, and it made the code symmetric with the qirr (queued interrupt
      for software generated interrupts), but now it is just extra and
      sometimes unneeded work to pass it down.
      Signed-off-by: NMilton Miller <miltonm@bga.com>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      d7cf0edb
  2. 02 10月, 2007 1 次提交
    • A
      [POWERPC] Fix xics set_affinity code · e48395f1
      Anton Blanchard 提交于
      On a POWER6 machine running 2.6.23-rc8 I sometimes see the following error:
      
      xics_set_affinity: No online cpus in the mask 00000000,00000000,00000000,00000001 for irq 20
      
      In a desperate attempt to get a changelog entry in 2.6.23, I took a look
      into it.
      
      It turns out we are passing a real and not a virtual irq into
      get_irq_server.  This works for the case where hwirq < NR_IRQS and we
      set virq = hwirq.  In my case however hwirq = 590082 and we try and
      access irq_desc[590082], slightly past the end at 512 entries.
      
      Lucky we ship lots of memory with our machines.
      Signed-off-by: NAnton Blanchard <anton@samba.org>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      e48395f1
  3. 13 9月, 2007 1 次提交
  4. 25 6月, 2007 1 次提交
    • M
      [POWERPC] Fix interrupt distribution in ppc970 · 7ccb4a66
      Mohan Kumar M 提交于
      In some of the PPC970 based systems, interrupt would be distributed to
      offline cpus also even when booted with "maxcpus=1".  So check whether
      cpu online map and cpu present map are equal or not.  If they are equal
      default_distrib_server is used as interrupt server otherwise boot cpu
      (default_server) used as interrupt server.
      
      In addition to this, if an interrupt is assigned to a specific cpu (ie
      smp affinity) and if that cpu is not online, the earlier code used to
      return the default_distrib_server as interrupt server.  This
      introduces an additional parameter to the get_irq function, called
      strict_check.  Based on this parameter, if the cpu is not online
      either default_distrib_server or -1 is returned.
      Signed-off-by: NMohan Kumar M <mohan@in.ibm.com>
      Cc: Michael Ellerman <michael@ellerman.id.au>
      Acked-by: NMilton Miller <miltonm@bga.com>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      7ccb4a66
  5. 02 6月, 2007 1 次提交
  6. 07 5月, 2007 1 次提交
  7. 13 4月, 2007 2 次提交
  8. 09 1月, 2007 1 次提交
  9. 04 12月, 2006 1 次提交
    • M
      [POWERPC] pSeries/kexec: Fix for interrupt distribution · a5715d6d
      Mohan Kumar M 提交于
      This allows any secondary CPU thread also to become boot cpu for
      POWER5.  The patch is required to solve kdump boot issue when the
      kdump kernel is booted with parameter "maxcpus=1".  XICS init code
      tries to match the current boot cpu id with "reg" property in each CPU
      node in the device tree.  But CPU node is created only for primary
      thread CPU ids and "reg" property only reflects primary CPU ids.  So
      when a kernel is booted on a secondary cpu thread above condition will
      never meet and the default distribution server is left as zero.  This
      leads to route the interrupts to CPU 0, but which is not online at
      this time.
      
      We use ibm,ppc-interrupt-server#s to check for both primary and
      secondary CPU ids.  Accordingly default distribution server value is
      initialized from "ibm,ppc-interrupt-gserver#s" property.  We loop
      through ibm,ppc-interrupt-gserver#s property to find the global
      distribution server from the last entry that matches with boot cpuid.
      Signed-off-by: NMohan Kumar M <mohan@in.ibm.com>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      a5715d6d
  10. 07 10月, 2006 1 次提交
  11. 05 10月, 2006 1 次提交
    • D
      IRQ: Maintain regs pointer globally rather than passing to IRQ handlers · 7d12e780
      David Howells 提交于
      Maintain a per-CPU global "struct pt_regs *" variable which can be used instead
      of passing regs around manually through all ~1800 interrupt handlers in the
      Linux kernel.
      
      The regs pointer is used in few places, but it potentially costs both stack
      space and code to pass it around.  On the FRV arch, removing the regs parameter
      from all the genirq function results in a 20% speed up of the IRQ exit path
      (ie: from leaving timer_interrupt() to leaving do_IRQ()).
      
      Where appropriate, an arch may override the generic storage facility and do
      something different with the variable.  On FRV, for instance, the address is
      maintained in GR28 at all times inside the kernel as part of general exception
      handling.
      
      Having looked over the code, it appears that the parameter may be handed down
      through up to twenty or so layers of functions.  Consider a USB character
      device attached to a USB hub, attached to a USB controller that posts its
      interrupts through a cascaded auxiliary interrupt controller.  A character
      device driver may want to pass regs to the sysrq handler through the input
      layer which adds another few layers of parameter passing.
      
      I've build this code with allyesconfig for x86_64 and i386.  I've runtested the
      main part of the code on FRV and i386, though I can't test most of the drivers.
      I've also done partial conversion for powerpc and MIPS - these at least compile
      with minimal configurations.
      
      This will affect all archs.  Mostly the changes should be relatively easy.
      Take do_IRQ(), store the regs pointer at the beginning, saving the old one:
      
      	struct pt_regs *old_regs = set_irq_regs(regs);
      
      And put the old one back at the end:
      
      	set_irq_regs(old_regs);
      
      Don't pass regs through to generic_handle_irq() or __do_IRQ().
      
      In timer_interrupt(), this sort of change will be necessary:
      
      	-	update_process_times(user_mode(regs));
      	-	profile_tick(CPU_PROFILING, regs);
      	+	update_process_times(user_mode(get_irq_regs()));
      	+	profile_tick(CPU_PROFILING);
      
      I'd like to move update_process_times()'s use of get_irq_regs() into itself,
      except that i386, alone of the archs, uses something other than user_mode().
      
      Some notes on the interrupt handling in the drivers:
      
       (*) input_dev() is now gone entirely.  The regs pointer is no longer stored in
           the input_dev struct.
      
       (*) finish_unlinks() in drivers/usb/host/ohci-q.c needs checking.  It does
           something different depending on whether it's been supplied with a regs
           pointer or not.
      
       (*) Various IRQ handler function pointers have been moved to type
           irq_handler_t.
      Signed-Off-By: NDavid Howells <dhowells@redhat.com>
      (cherry picked from 1b16e7ac850969f38b375e511e3fa2f474a33867 commit)
      7d12e780
  12. 08 8月, 2006 1 次提交
    • H
      [POWERPC] Fix might-sleep warning on removing cpus · 81b73dd9
      Haren Myneni 提交于
      Noticing the following might_sleep warning (dump_stack()) during kdump
      testing when CONFIG_DEBUG_SPINLOCK_SLEEP is enabled. All secondary CPUs
      will be calling rtas_set_indicator with interrupts disabled to remove
      them from global interrupt queue.
      
      BUG: sleeping function called from invalid context at
      arch/powerpc/kernel/rtas.c:463
      in_atomic():1, irqs_disabled():1
      Call Trace:
      [C00000000FFFB970] [C000000000010234] .show_stack+0x68/0x1b0 (unreliable)
      [C00000000FFFBA10] [C000000000059354] .__might_sleep+0xd8/0xf4
      [C00000000FFFBA90] [C00000000001D1BC] .rtas_busy_delay+0x20/0x5c
      [C00000000FFFBB20] [C00000000001D8A8] .rtas_set_indicator+0x6c/0xcc
      [C00000000FFFBBC0] [C000000000048BF4] .xics_teardown_cpu+0x118/0x134
      [C00000000FFFBC40] [C00000000004539C]
      .pseries_kexec_cpu_down_xics+0x74/0x8c
      [C00000000FFFBCC0] [C00000000002DF08] .crash_ipi_callback+0x15c/0x188
      [C00000000FFFBD50] [C0000000000296EC] .smp_message_recv+0x84/0xdc
      [C00000000FFFBDC0] [C000000000048E08] .xics_ipi_dispatch+0xf0/0x130
      [C00000000FFFBE50] [C00000000009EF10] .handle_IRQ_event+0x7c/0xf8
      [C00000000FFFBF00] [C0000000000A0A14] .handle_percpu_irq+0x90/0x10c
      [C00000000FFFBF90] [C00000000002659C] .call_handle_irq+0x1c/0x2c
      [C00000000058B9C0] [C00000000000CA10] .do_IRQ+0xf4/0x1a4
      [C00000000058BA50] [C0000000000044EC] hardware_interrupt_entry+0xc/0x10
       --- Exception: 501 at .plpar_hcall_norets+0x14/0x1c
         LR = .pseries_dedicated_idle_sleep+0x190/0x1d4
      [C00000000058BD40] [C00000000058BDE0] 0xc00000000058bde0 (unreliable)
      [C00000000058BDF0] [C00000000001270C] .cpu_idle+0x10c/0x1e0
      [C00000000058BE70] [C000000000009274] .rest_init+0x44/0x5c
      
      To fix this issue, rtas_set_indicator_fast() is added so that will not
      wait for RTAS 'busy' delay and this new function is used for kdump (in
      xics_teardown_cpu()) and for CPU hotplug ( xics_migrate_irqs_away() and
      xics_setup_cpu()).
      
      Note that the platform architecture spec says that set-indicator
      on the indicator we're using here is not permitted to return the
      busy or extended busy status codes.
      Signed-off-by: NHaren Myneni <haren@us.ibm.com>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      81b73dd9
  13. 01 8月, 2006 1 次提交
    • A
      [POWERPC] clean up pseries hcall interfaces · b9377ffc
      Anton Blanchard 提交于
      Our pseries hcall interfaces are out of control:
      
      	plpar_hcall_norets
      	plpar_hcall
      	plpar_hcall_8arg_2ret
      	plpar_hcall_4out
      	plpar_hcall_7arg_7ret
      	plpar_hcall_9arg_9ret
      
      Create 3 interfaces to cover all cases:
      
      	plpar_hcall_norets:	7 arguments no returns
      	plpar_hcall:		6 arguments 4 returns
      	plpar_hcall9:		9 arguments 9 returns
      
      There are only 2 cases in the kernel that need plpar_hcall9, hopefully
      we can keep it that way.
      
      Pass in a buffer to stash return parameters so we avoid the &dummy1,
      &dummy2 madness.
      Signed-off-by: NAnton Blanchard <anton@samba.org>
      --
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      b9377ffc
  14. 31 7月, 2006 1 次提交
  15. 11 7月, 2006 1 次提交
    • B
      [PATCH] powerpc: fix trigger handling in the new irq code · 6e99e458
      Benjamin Herrenschmidt 提交于
      This patch slightly reworks the new irq code to fix a small design error.  I
      removed the passing of the trigger to the map() calls entirely, it was not a
      good idea to have one call do two different things.  It also fixes a couple of
      corner cases.
      
      Mapping a linux virtual irq to a physical irq now does only that.  Setting the
      trigger is a different action which has a different call.
      
      The main changes are:
      
      - I no longer call host->ops->map() for an already mapped irq, I just return
        the virtual number that was already mapped.  It was called before to give an
        opportunity to change the trigger, but that was causing issues as that could
        happen while the interrupt was in use by a device, and because of the
        trigger change, map would potentially muck around with things in a racy way.
         That was causing much burden on a given's controller implementation of
        map() to get it right.  This is much simpler now.  map() is only called on
        the initial mapping of an irq, meaning that you know that this irq is _not_
        being used.  You can initialize the hardware if you want (though you don't
        have to).
      
      - Controllers that can handle different type of triggers (level/edge/etc...)
        now implement the standard irq_chip->set_type() call as defined by the
        generic code.  That means that you can use the standard set_irq_type() to
        configure an irq line manually if you wish or (though I don't like that
        interface), pass explicit trigger flags to request_irq() as defined by the
        generic kernel interfaces.  Also, using those interfaces guarantees that
        your controller set_type callback is called with the descriptor lock held,
        thus providing locking against activity on the same interrupt (including
        mask/unmask/etc...) automatically.  A result is that, for example, MPIC's
        own map() implementation calls irq_set_type(NONE) to configure the hardware
        to the default triggers.
      
      - To allow the above, the irq_map array entry for the new mapped interrupt
        is now set before map() callback is called for the controller.
      
      - The irq_create_of_mapping() (also used by irq_of_parse_and_map()) function
        for mapping interrupts from the device-tree now also call the separate
        set_irq_type(), and only does so if there is a change in the trigger type.
      
      - While I was at it, I changed pci_read_irq_line() (which is the helper I
        would expect most archs to use in their pcibios_fixup() to get the PCI
        interrupt routing from the device tree) to also handle a fallback when the
        DT mapping fails consisting of reading the PCI_INTERRUPT_PIN to know wether
        the device has an interrupt at all, and the the PCI_INTERRUPT_LINE to get an
        interrupt number from the device.  That number is then mapped using the
        default controller, and the trigger is set to level low.  That default
        behaviour works for several platforms that don't have a proper interrupt
        tree like Pegasos.  If it doesn't work for your platform, then either
        provide a proper interrupt tree from the firmware so that fallback isn't
        needed, or don't call pci_read_irq_line()
      
      - Add back a bit that got dropped by my main rework patch for properly
        clearing pending IPIs on pSeries when using a kexec
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Paul Mackerras <paulus@samba.org>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      6e99e458
  16. 03 7月, 2006 3 次提交
    • B
      [POWERPC] Add new interrupt mapping core and change platforms to use it · 0ebfff14
      Benjamin Herrenschmidt 提交于
      This adds the new irq remapper core and removes the old one.  Because
      there are some fundamental conflicts with the old code, like the value
      of NO_IRQ which I'm now setting to 0 (as per discussions with Linus),
      etc..., this commit also changes the relevant platform and driver code
      over to use the new remapper (so as not to cause difficulties later
      in bisecting).
      
      This patch removes the old pre-parsing of the open firmware interrupt
      tree along with all the bogus assumptions it made to try to renumber
      interrupts according to the platform. This is all to be handled by the
      new code now.
      
      For the pSeries XICS interrupt controller, a single remapper host is
      created for the whole machine regardless of how many interrupt
      presentation and source controllers are found, and it's set to match
      any device node that isn't a 8259.  That works fine on pSeries and
      avoids having to deal with some of the complexities of split source
      controllers vs. presentation controllers in the pSeries device trees.
      
      The powerpc i8259 PIC driver now always requests the legacy interrupt
      range. It also has the feature of being able to match any device node
      (including NULL) if passed no device node as an input. That will help
      porting over platforms with broken device-trees like Pegasos who don't
      have a proper interrupt tree.
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      0ebfff14
    • B
      [POWERPC] Use the genirq framework · b9e5b4e6
      Benjamin Herrenschmidt 提交于
      This adapts the generic powerpc interrupt handling code, and all of
      the platforms except for the embedded 6xx machines, to use the new
      genirq framework.
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      b9e5b4e6
    • T
      [PATCH] irq-flags: POWERPC: Use the new IRQF_ constants · 6714465e
      Thomas Gleixner 提交于
      Use the new IRQF_ constants and remove the SA_INTERRUPT define
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: "David S. Miller" <davem@davemloft.net>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      6714465e
  17. 01 7月, 2006 1 次提交
  18. 30 6月, 2006 2 次提交
    • I
      [PATCH] genirq: cleanup: merge irq_affinity[] into irq_desc[] · a53da52f
      Ingo Molnar 提交于
      Consolidation: remove the irq_affinity[NR_IRQS] array and move it into the
      irq_desc[NR_IRQS].affinity field.
      
      [akpm@osdl.org: sparc64 build fix]
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      a53da52f
    • I
      [PATCH] genirq: rename desc->handler to desc->chip · d1bef4ed
      Ingo Molnar 提交于
      This patch-queue improves the generic IRQ layer to be truly generic, by adding
      various abstractions and features to it, without impacting existing
      functionality.
      
      While the queue can be best described as "fix and improve everything in the
      generic IRQ layer that we could think of", and thus it consists of many
      smaller features and lots of cleanups, the one feature that stands out most is
      the new 'irq chip' abstraction.
      
      The irq-chip abstraction is about describing and coding and IRQ controller
      driver by mapping its raw hardware capabilities [and quirks, if needed] in a
      straightforward way, without having to think about "IRQ flow"
      (level/edge/etc.) type of details.
      
      This stands in contrast with the current 'irq-type' model of genirq
      architectures, which 'mixes' raw hardware capabilities with 'flow' details.
      The patchset supports both types of irq controller designs at once, and
      converts i386 and x86_64 to the new irq-chip design.
      
      As a bonus side-effect of the irq-chip approach, chained interrupt controllers
      (master/slave PIC constructs, etc.) are now supported by design as well.
      
      The end result of this patchset intends to be simpler architecture-level code
      and more consolidation between architectures.
      
      We reused many bits of code and many concepts from Russell King's ARM IRQ
      layer, the merging of which was one of the motivations for this patchset.
      
      This patch:
      
      rename desc->handler to desc->chip.
      
      Originally i did not want to do this, because it's a big patch.  But having
      both "desc->handler", "desc->handle_irq" and "action->handler" caused a
      large degree of confusion and made the code appear alot less clean than it
      truly is.
      
      I have also attempted a dual approach as well by introducing a
      desc->chip alias - but that just wasnt robust enough and broke
      frequently.
      
      So lets get over with this quickly.  The conversion was done automatically
      via scripts and converts all the code in the kernel.
      
      This renaming patch is the first one amongst the patches, so that the
      remaining patches can stay flexible and can be merged and split up
      without having some big monolithic patch act as a merge barrier.
      
      [akpm@osdl.org: build fix]
      [akpm@osdl.org: another build fix]
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      d1bef4ed
  19. 22 4月, 2006 2 次提交
    • O
      [PATCH] powerpc: Lack of ISA interrupts on XICS isn't dangerous · cc98f705
      Olof Johansson 提交于
      This isn't really a dangerous thing any more; most systems lack
      ISA interrupt controllers.
      Signed-off-by: NOlof Johansson <olof@lixom.net>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      cc98f705
    • H
      [PATCH] powerpc: clear IPIs on kdump · 81bbbe92
      Haren Myneni 提交于
      In some crash scenarios, the kexec CPU is not responding to an IPI sent by
      secondary CPU after init thread is forked, causing the system to drop into
      xmon during kdump boot.  This problem can be reproduced each time when the
      debugger is enabled and soft-reset is used to invoke kdump boot. The first
      CPU sends an IPI - setting the IPI priority for all secondary cpus
      (xics_cause_ipi()). But some CPUs will enter into the xmon via soft-reset,
      i.e, not executing xics_ipi_action(). Hence, IPI is not cleared. When
      exited from the debugger, one of these CPUs could become the primary kexec
      CPU. Since the IPI is not cleared, causing this issue in kdump boot. This
      patch clears and EOI IPI for kexec CPU as well before the kdump boot
      started.
      Signed-off-by: NHaren Myneni <haren@us.ibm.com>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      81bbbe92
  20. 01 4月, 2006 1 次提交
  21. 29 3月, 2006 1 次提交
  22. 27 3月, 2006 1 次提交
    • A
      [PATCH] powerpc: Allow non zero boot cpuids · 4df20460
      Anton Blanchard 提交于
      We currently have a hack to flip the boot cpu and its secondary thread
      to logical cpuid 0 and 1. This means the logical - physical mapping will
      differ depending on which cpu is boot cpu. This is most apparent on
      kexec, where we might kexec on any cpu and therefore change the mapping
      from boot to boot.
      
      The patch below does a first pass early on to work out the logical cpuid
      of the boot thread. We then fix up some paca structures to match.
      
      Ive also removed the boot_cpuid_phys variable for ppc64, to be
      consistent we use get_hard_smp_processor_id(boot_cpuid) everywhere.
      Signed-off-by: NAnton Blanchard <anton@samba.org>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      4df20460
  23. 22 3月, 2006 1 次提交
  24. 12 1月, 2006 1 次提交
  25. 09 1月, 2006 1 次提交
  26. 22 12月, 2005 1 次提交
    • P
      powerpc: Fix i8259 cascade on pSeries with XICS interrupt controller · 8b1af56b
      Paul Mackerras 提交于
      It turns out that commit f9bd170a
      broke the cascade from XICS to i8259 on pSeries machines; specifically
      we ended up not ever doing the EOI on the XICS for the cascade.  The
      result was that interrupts from the serial ports (and presumably any
      other devices using ISA interrupts) didn't get through.  This fixes
      it and also simplifies the code, by doing the EOI on the XICS in the
      xics_get_irq routine after reading and acking the interrupt on the
      i8259.
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      8b1af56b
  27. 10 11月, 2005 1 次提交
  28. 09 11月, 2005 1 次提交
  29. 28 10月, 2005 2 次提交
  30. 12 9月, 2005 1 次提交
  31. 05 8月, 2005 1 次提交
  32. 26 6月, 2005 1 次提交
    • R
      [PATCH] ppc64: kexec support for ppc64 · fce0d574
      R Sharada 提交于
      This patch implements the kexec support for ppc64 platforms.
      
      A couple of notes:
      
      1)  We copy the pages in virtual mode, using the full base kernel
          and a statically allocated stack.   At kexec_prepare time we
          scan the pages and if any overlap our (0, _end[]) range we
          return -ETXTBSY.
      
          On PowerPC 64 systems running in LPAR (logical partitioning)
          mode, only a small region of memory, referred to as the RMO,
          can be accessed in real mode.  Since Linux runs with only one
          zone of memory in the memory allocator, and it can be orders of
          magnitude more memory than the RMO, looping until we allocate
          pages in the source region is not feasible.  Copying in virtual
          means we don't have to write a hash table generation and call
          hypervisor to insert translations, instead we rely on the pinned
          kernel linear mapping.  The kernel already has move to linked
          location built in, so there is no requirement to load it at 0.
      
          If we want to load something other than a kernel, then a stub
          can be written to copy a linear chunk in real mode.
      
      2)  The start entry point gets passed parameters from the kernel.
          Slaves are started at a fixed address after copying code from
          the entry point.
      
          All CPUs get passed their firmware assigned physical id in r3
          (most calling conventions use this register for the first
          argument).
      
          This is used to distinguish each CPU from all other CPUs.
          Since firmware is not around, there is no other way to obtain
          this information other than to pass it somewhere.
      
          A single CPU, referred to here as the master and the one executing
          the kexec call, branches to start with the address of start in r4.
          While this can be calculated, we have to load it through a gpr to
          branch to this point so defining the register this is contained
          in is free.  A stack of unspecified size is available at r1
          (also common calling convention).
      
          All remaining running CPUs are sent to start at absolute address
          0x60 after copying the first 0x100 bytes from start to address 0.
          This convention was chosen because it matches what the kernel
          has been doing itself.  (only gpr3 is defined).
      
          Note: This is not quite the convention of the kexec bootblock v2
          in the kernel.  A stub has been written to convert between them,
          and we may adjust the kernel in the future to allow this directly
          without any stub.
      
      3)  Destination pages can be placed anywhere, even where they
          would not be accessible in real mode.  This will allow us to
          place ram disks above the RMO if we choose.
      Signed-off-by: NMilton Miller <miltonm@bga.com>
      Signed-off-by: NR Sharada <sharada@in.ibm.com>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      fce0d574
  33. 06 5月, 2005 1 次提交
  34. 17 4月, 2005 1 次提交
    • L
      Linux-2.6.12-rc2 · 1da177e4
      Linus Torvalds 提交于
      Initial git repository build. I'm not bothering with the full history,
      even though we have it. We can create a separate "historical" git
      archive of that later if we want to, and in the meantime it's about
      3.2GB when imported into git - space that would just make the early
      git days unnecessarily complicated, when we don't have a lot of good
      infrastructure for it.
      
      Let it rip!
      1da177e4