Add i.MX8M Plus specific soc data, the max register is FSL_SAI_MDIV.
Signed-off-by: NShengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: NFabio Estevam <festevam@gmail.com>
Link: https://lore.kernel.org/r/1652688372-10274-3-git-send-email-shengjiu.wang@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>

On i.MX8MM the max register is FSL_SAI_MCTL, which is
different with previous platform, so add max_register in
soc data to distinguish platforms.
And add specific soc data for i.MX8MM
Signed-off-by: NShengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: NFabio Estevam <festevam@gmail.com>
Link: https://lore.kernel.org/r/1652688372-10274-2-git-send-email-shengjiu.wang@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>

Refactoring in commit a50b7926 ("ASoC: fsl_sai: implement 1:1
bclk:mclk ratio support") led to the bypass never happening
as (ratio = 1) was caught in the existing if (ratio & 1) continue;
check. The correct check sequence instead is:

 - skip all ratios lower than one and higher than 512
 - skip all odd ratios except for 1:1
 - skip 1:1 ratio if and only if !support_1_1_ratio

And for all others, calculate the appropriate divider. Adjust the
code to facilitate this.

Fixes: a50b7926 ("ASoC: fsl_sai: implement 1:1 bclk:mclk ratio support")
Signed-off-by: NAhmad Fatoum <a.fatoum@pengutronix.de>
Acked-by: NShengjiu Wang <shengjiu.wang@gmail.com>
Reviewed-by: NSascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.kernel.org/r/20220405155731.745413-1-a.fatoum@pengutronix.deSigned-off-by: NMark Brown <broonie@kernel.org>

With higher channel counts, we may need higher clock rates.  Starting
with SAI v3.1 (i.MX8MM), we can bypass the divider and get a 1:1
bclk:mclk ratio. Add the necessary support.
Signed-off-by: NViorel Suman <viorel.suman@nxp.com>
Signed-off-by: NAhmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.kernel.org/r/20220302083428.3804687-8-s.hauer@pengutronix.deSigned-off-by: NMark Brown <broonie@kernel.org>

In fsl_sai_set_bclk() we want to calculate the divider that gets us
closest to the desired frequency, so use DIV_ROUND_CLOSEST() instead of
just doing a clk_rate/freq.
Also discard invalid ratios earlier.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.kernel.org/r/20220302083428.3804687-7-s.hauer@pengutronix.deSigned-off-by: NMark Brown <broonie@kernel.org>

"ret" is normally used as a variable name for return values. In
fsl_sai_set_bclk() it stores the difference between the desired rate and
the rate we can archieve, so rename it to "diff". Also rename "savesub"
to "bestdiff" as that stores the best difference we have found.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.kernel.org/r/20220302083428.3804687-6-s.hauer@pengutronix.deSigned-off-by: NMark Brown <broonie@kernel.org>

The driver tests for the hardware revision being newer than 3.1
with (sai->verid.major >= 3 && sai->verid.minor >= 1). The result
is obviously wrong for hardware revision 4.0. Fix this by storing
the full version in a single variable and comparing to that one.
No practical change at the moment as there is no 4.0 ip version
currently.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.kernel.org/r/20220302083428.3804687-5-s.hauer@pengutronix.deSigned-off-by: NMark Brown <broonie@kernel.org>

Depending on SAI synchronization mode, the same value is either
written to FSL_SAI_TCR2 or FSL_SAI_RCR2 or nothing is written at all.

As the computation is the same either way, factor it out to make it
clearer what the difference is. No functional change.
Signed-off-by: NAhmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.kernel.org/r/20220302083428.3804687-4-s.hauer@pengutronix.deSigned-off-by: NMark Brown <broonie@kernel.org>

Instead of using a boolean "irq_none" to describe the interrupt
handlers return value use a variable of type irqreturn_t and return
it directly. No functional change.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.kernel.org/r/20220302083428.3804687-3-s.hauer@pengutronix.deSigned-off-by: NMark Brown <broonie@kernel.org>

The fsl_sai driver has FSL_FMT_TRANSMITTER and FSL_FMT_RECEIVER defines
which are used in a single function only then are then only translated
into a bool 'tx' variable. Drop the defines and pass the boolean value
directly to fsl_sai_set_dai_sysclk_tr(). No functional change.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.kernel.org/r/20220302083428.3804687-2-s.hauer@pengutronix.deSigned-off-by: NMark Brown <broonie@kernel.org>

Since 70d435ba ("ASoC: imx-pcm-dma: simplify pcm_config") the size
argument to imx_pcm_dma_init() is unused, so drop it. Also remove the
now unused defines that the users of imx_pcm_dma_init() used to pass the
size argument
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.kernel.org/r/20220223130625.3430589-1-s.hauer@pengutronix.deSigned-off-by: NMark Brown <broonie@kernel.org>

The fsl_sai driver calculates the number of pins used and enables
multiple channels if necessary. This means the SAI expects data in
one FIFO per pin. The SDMA engine only services a single FIFO, so
multi pin support doesn't work at all.

This patch enables the software combine mode in chips that support
it. With this the SAI presents only a single FIFO to the outside
and distributes the data into the different FIFOs internally.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.kernel.org/r/20220111081518.982437-1-s.hauer@pengutronix.deSigned-off-by: NMark Brown <broonie@kernel.org>

As part of moving to remove the old style defines for the bus clocks update
the fsl_sai driver to use more modern terminology for clocking.
Signed-off-by: NMark Brown <broonie@kernel.org>
Reviewed-by: NFabio Estevam <festevam@gmail.com>
Link: https://lore.kernel.org/r/20210921213542.31688-6-broonie@kernel.orgSigned-off-by: NMark Brown <broonie@kernel.org>

There is no defer probe when adding platform component to
snd_soc_pcm_runtime(rtd), the code is in snd_soc_add_pcm_runtime()

snd_soc_register_card()
  -> snd_soc_bind_card()
    -> snd_soc_add_pcm_runtime()
      -> adding cpu dai
      -> adding codec dai
      -> adding platform component.

So if the platform component is not ready at that time, then the
sound card still registered successfully, but platform component
is empty, the sound card can't be used.

As there is defer probe checking for cpu dai component, then register
platform component before cpu dai to avoid such issue.

Fixes: 43550821 ("ASoC: Add SAI SoC Digital Audio Interface driver")
Signed-off-by: NShengjiu Wang <shengjiu.wang@nxp.com>
Link: https://lore.kernel.org/r/1630665006-31437-2-git-send-email-shengjiu.wang@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>

Use devm_platform_get_and_ioremap_resource() to simplify
code.
Signed-off-by: NYang Yingliang <yangyingliang@huawei.com>
Link: https://lore.kernel.org/r/20210615013922.784296-7-yangyingliang@huawei.comSigned-off-by: NMark Brown <broonie@kernel.org>

When there is power domain bind with bus clock,

The call flow:
devm_regmap_init_mmio_clk
   - clk_prepare()
      - clk_pm_runtime_get()

cause the power domain of clock always be enabled after
regmap_init(). which impact the power consumption.

So use devm_regmap_init_mmio instead of
devm_regmap_init_mmio_clk, then explicitly enable clock when
using by pm_runtime_get(), if CONFIG_PM=n, then
fsl_sai_runtime_resume will be explicitly called.
Signed-off-by: NShengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: NViorel Suman <viorel.suman@nxp.com>
Link: https://lore.kernel.org/r/1616141203-13344-1-git-send-email-shengjiu.wang@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>

On SoCs such as i.MX7ULP, cpuidle has some levels which
may disable system/bus clocks, so need to add pm_qos to
prevent cpuidle from entering low level idles and make sure
system/bus clocks are enabled when sai is active.
Signed-off-by: NShengjiu Wang <shengjiu.wang@nxp.com>
Link: https://lore.kernel.org/r/1613983220-5373-1-git-send-email-shengjiu.wang@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>

snd_soc_dai_set_drvdata is not needed when the set data comes from
snd_soc_dai_get_drvdata or dev_get_drvdata.  The problem was fixed
usingthe following semantic patch: (http://coccinelle.lip6.fr/)

// <smpl>
@@
expression x,y,e;
@@
	x = dev_get_drvdata(y->dev)
	... when != x = e
-	snd_soc_dai_set_drvdata(y,x);

@@
expression x,y,e;
@@
	x = snd_soc_dai_get_drvdata(y)
	... when != x = e
-	snd_soc_dai_set_drvdata(y,x);
// </smpl>
Signed-off-by: NJulia Lawall <Julia.Lawall@inria.fr>
Acked-by: NNicolin Chen <nicoleotsuka@gmail.com>
Link: https://lore.kernel.org/r/20210213101907.1318496-5-Julia.Lawall@inria.frSigned-off-by: NMark Brown <broonie@kernel.org>

This patch syncs naming rule.

 - xxx_rates;
 + xxx_rate;

 - xxx_samplebits;
 + xxx_sample_bits;
Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87eeimolh5.wl-kuninori.morimoto.gx@renesas.comSigned-off-by: NMark Brown <broonie@kernel.org>

On VF610, mclk0 = bus_clk;
On i.MX6SX/6UL/6ULL/7D, mclk0 = mclk1;
On i.MX7ULP, mclk0 = bus_clk;
On i.MX8QM/8QXP, mclk0 = bus_clk;
On i.MX8MQ/8MN/8MM/8MP, mclk0 = bus_clk;

So add variable mclk0_is_mclk1 in fsl_sai_soc_data to
distinguish these platforms.
Signed-off-by: NShengjiu Wang <shengjiu.wang@nxp.com>
Acked-by: NNicolin Chen <nicoleotsuka@gmail.com>
Link: https://lore.kernel.org/r/1605768038-4582-1-git-send-email-shengjiu.wang@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>

Instantiate snd_soc_dai_driver for independent symmetric control.
Otherwise the symmetric setting may be overwritten by other
instance.

Fixes: 08fdf65e ("ASoC: fsl_sai: Add asynchronous mode support")
Signed-off-by: NShengjiu Wang <shengjiu.wang@nxp.com>
Link: https://lore.kernel.org/r/1600424760-32071-1-git-send-email-shengjiu.wang@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>

SAI support select MCLK direction with version.major > 3
and version.minor > 1, the default direction is input,
set it to be output according to DT property.
Signed-off-by: NShengjiu Wang <shengjiu.wang@nxp.com>
Acked-by: NNicolin Chen <nicoleotsuka@gmail.com>
Reviewed-by: NFabio Estevam <festevam@gmail.com>
Link: https://lore.kernel.org/r/1600323079-5317-4-git-send-email-shengjiu.wang@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>

fsl_sai_check_version can help to parse the version info
in VERID and PARAM registers.
Signed-off-by: NShengjiu Wang <shengjiu.wang@nxp.com>
Acked-by: NNicolin Chen <nicoleotsuka@gmail.com>
Reviewed-by: NFabio Estevam <festevam@gmail.com>
Link: https://lore.kernel.org/r/1600323079-5317-3-git-send-email-shengjiu.wang@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>

On i.MX8MQ/i.MX8MN/i.MX8MM platform, the sai IP is upgraded.
There are some new registers and new bit definition. This
patch is to complete the register list.
Signed-off-by: NShengjiu Wang <shengjiu.wang@nxp.com>
Acked-by: NNicolin Chen <nicoleotsuka@gmail.com>
Reviewed-by: NFabio Estevam <festevam@gmail.com>
Link: https://lore.kernel.org/r/1600323079-5317-2-git-send-email-shengjiu.wang@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>

Transmit data pins will output zero when slots are masked or channels
are disabled. In CHMOD TDM mode, transmit data pins are tri-stated when
slots are masked or channels are disabled. When data pins are tri-stated,
there is noise on some channels when FS clock value is high and data is
read while fsclk is transitioning from high to low.
Signed-off-by: NCosmin-Gabriel Samoila <cosmin.samoila@nxp.com>
Signed-off-by: NShengjiu Wang <shengjiu.wang@nxp.com>
Acked-by: NNicolin Chen <nicoleotsuka@gmail.com>
Link: https://lore.kernel.org/r/1599112427-22038-1-git-send-email-shengjiu.wang@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>

One data channel is one data line. From imx7ulp, the SAI IP is
enhanced to support multiple data channels.

If there is only two channels input and slots is 2, then enable one
data channel is enough for data transfer. So enable the TCE/RCE and
transmit/receive mask register according to the input channels and
slots configuration.

Move the data channel enablement from startup() to hw_params().
Signed-off-by: NShengjiu Wang <shengjiu.wang@nxp.com>
Acked-by: NNicolin Chen <nicoleotsuka@gmail.com>
Link: https://lore.kernel.org/r/1598958068-10552-1-git-send-email-shengjiu.wang@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>

Regmap initialization may return -EPROBE_DEFER for clock
may not be ready, so check -EPROBE_DEFER error type before
start another Regmap initialization.
Signed-off-by: NShengjiu Wang <shengjiu.wang@nxp.com>
Acked-by: NNicolin Chen <nicoleotsuka@gmail.com>
Link: https://lore.kernel.org/r/1598255887-1391-1-git-send-email-shengjiu.wang@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>

As new function fsl_sai_dir_is_synced is included for checking if
stream is synced by the opposite stream, then replace the existing
synchronous checking with this new function.
Signed-off-by: NShengjiu Wang <shengjiu.wang@nxp.com>
Acked-by: NNicolin Chen <nicoleotsuka@gmail.com>
Link: https://lore.kernel.org/r/20200805063413.4610-4-shengjiu.wang@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>

Tx synchronous with Rx: The RMR is the word mask register, it is used
to mask any word in the frame, it is not relating to clock generation,
So it is no need to be changed when Tx is going to be enabled.

Rx synchronous with Tx: The TMR is the word mask register, it is used
to mask any word in the frame, it is not relating to clock generation,
So it is no need to be changed when Rx is going to be enabled.
Signed-off-by: NShengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: NNicolin Chen <nicoleotsuka@gmail.com>
Link: https://lore.kernel.org/r/20200805063413.4610-3-shengjiu.wang@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>

Current code enables TCSR.TE and RCSR.RE together, and disable
TCSR.TE and RCSR.RE together in trigger(), which only supports
one operation mode：
1. Rx synchronous with Tx: TE is last enabled and first disabled

Other operation mode need to be considered also:
2. Tx synchronous with Rx: RE is last enabled and first disabled.
3. Asynchronous mode: Tx and Rx are independent.

So the enable TCSR.TE and RCSR.RE sequence and the disable
sequence need to be refined accordingly for #2 and #3.

There is slightly against what RM recommennds with this change.
For example in Rx synchronous with Tx mode, case "aplay 1.wav;
arecord 2.wav" enable TE before RE. But it should be safe to
do so, judging by years of testing results.
Signed-off-by: NShengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: NNicolin Chen <nicoleotsuka@gmail.com>
Link: https://lore.kernel.org/r/20200805063413.4610-2-shengjiu.wang@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>

The fifo_depth is 64 on i.MX8QM/i.MX8QXP, 128 on i.MX8MQ, 16 on
i.MX7ULP.

Original FSL_SAI_CR1_RFW_MASK value 0x1F is not suitable for
these platform, the FIFO watermark mask should be updated
according to the fifo_depth.

Fixes: a860fac4 ("ASoC: fsl_sai: Add support for imx7ulp/imx8mq")
Signed-off-by: NShengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: NFabio Estevam <festevam@gmail.com>
Link: https://lore.kernel.org/r/1596176895-28724-1-git-send-email-shengjiu.wang@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>

When there is dedicated power domain bound with device, after probing
the power will be disabled, then registers are not accessible in
fsl_sai_dai_probe(), so regcache only need to be enabled in end of
probe() and regcache_mark_dirty should be moved to pm runtime resume
callback function.
Signed-off-by: NShengjiu Wang <shengjiu.wang@nxp.com>
Acked-by: NNicolin Chen <nicoleotsuka@gmail.com>
Link: https://lore.kernel.org/r/1593412953-10897-1-git-send-email-shengjiu.wang@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>

If the imx-sdma driver is built as a module, the fsl-sai device doesn't
disable on probing failure, which causes the warning in the next probing:

==================================================================
fsl-sai 308a0000.sai: Unbalanced pm_runtime_enable!
fsl-sai 308a0000.sai: Unbalanced pm_runtime_enable!
fsl-sai 308a0000.sai: Unbalanced pm_runtime_enable!
fsl-sai 308a0000.sai: Unbalanced pm_runtime_enable!
fsl-sai 308a0000.sai: Unbalanced pm_runtime_enable!
fsl-sai 308a0000.sai: Unbalanced pm_runtime_enable!
==================================================================

Disabling the device properly fixes the issue.

Fixes: 812ad463 ("ASoC: fsl_sai: Add support for runtime pm")
Signed-off-by: NOleksandr Suvorov <oleksandr.suvorov@toradex.com>
Link: https://lore.kernel.org/r/20200205160436.3813642-1-oleksandr.suvorov@toradex.comSigned-off-by: NMark Brown <broonie@kernel.org>

The LS1028A SoC uses the same interrupt line for adjacent SAIs. Use
IRQF_SHARED to be able to use these SAIs simultaneously.
Signed-off-by: NMichael Walle <michael@walle.cc>
Reviewed-by: NFabio Estevam <festevam@gmail.com>
Acked-by: NNicolin Chen <nicoleotsuka@gmail.com>
Acked-by: NDaniel Baluta <daniel.baluta@nxp.com>
Link: https://lore.kernel.org/r/20191128223802.18228-1-michael@walle.ccSigned-off-by: NMark Brown <broonie@kernel.org>

EDMA requires the period size to be multiple of maxburst. Otherwise the
remaining bytes are not transferred and thus noise is produced.

We can handle this issue by adding a constraint on
SNDRV_PCM_HW_PARAM_PERIOD_SIZE to be multiple of tx/rx maxburst value.
Signed-off-by: NMihai Serban <mihai.serban@nxp.com>
Signed-off-by: NDaniel Baluta <daniel.baluta@nxp.com>
Acked-by: NNicolin Chen <nicoleotsuka@gmail.com>
Link: https://lore.kernel.org/r/20190913192807.8423-2-daniel.baluta@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>

This is to allow machine drivers to set a certain bitclk rate
which might not be exactly rate * frame size.

Cc: NXP Linux Team <linux-imx@nxp.com>
Signed-off-by: NViorel Suman <viorel.suman@nxp.com>
Signed-off-by: NDaniel Baluta <daniel.baluta@nxp.com>
Acked-by: NNicolin Chen <nicoleotsuka@gmail.com>
Link: https://lore.kernel.org/r/20190830215910.31590-1-daniel.baluta@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>

SAI module on imx8qm features a register map similar with imx6 series
(it doesn't have VERID and PARAM registers at the beginning
of address spece).

Also, it has one FIFO which can help up to 64 * 32 bit samples.
Signed-off-by: NDaniel Baluta <daniel.baluta@nxp.com>
Link: https://lore.kernel.org/r/20190814082911.665-2-daniel.baluta@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>

SAI module on imx7ulp/imx8m features 2 new registers (VERID and PARAM)
at the beginning of register address space.

On imx7ulp FIFOs can held up to 16 x 32 bit samples.
On imx8mq FIFOs can held up to 128 x 32 bit samples.
Signed-off-by: NDaniel Baluta <daniel.baluta@nxp.com>
Acked-by: NNicolin Chen <nicoleotsuka@gmail.com>
Link: https://lore.kernel.org/r/20190806151214.6783-5-daniel.baluta@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>

New IP version introduces Version ID and Parameter registers
and optionally added Timestamp feature.

VERID and PARAM registers are placed at the top of registers
address space and some registers are shifted according to
the following table:

Tx/Rx data registers and Tx/Rx FIFO registers keep their
addresses, all other registers are shifted by 8.

SAI Memory map is described in chapter 13.10.4.1.1 I2S Memory map
of the Reference Manual [1].

In order to make as less changes as possible we attach an offset
to each register offset to each changed register definition. The
offset is read from each board private data.

[1]https://cache.nxp.com/secured/assets/documents/en/reference-manual/IMX8MDQLQRM.pdf?__gda__=1563728701_38bea7f0f726472cc675cb141b91bec7&fileExt=.pdfSigned-off-by: NMihai Serban <mihai.serban@nxp.com>
[initial coding in the NXP internal tree]
Signed-off-by: NShengjiu Wang <shengjiu.wang@nxp.com>
[bugfixing and cleanups]
Signed-off-by: NDaniel Baluta <daniel.baluta@nxp.com>
[adapted to linux-next]
Acked-by: NNicolin Chen <nicoleotsuka@gmail.com>
Link: https://lore.kernel.org/r/20190806151214.6783-4-daniel.baluta@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>

Tx channel enable (TCE) / Rx channel enable (RCE) bits
enable corresponding data channel for Tx/Rx operation.

Because SAI supports up the 8 channels TCE/RCE occupy
up the 8 bits inside TCR3/RCR3 registers we need to extend
the mask to reflect this.
Signed-off-by: NDaniel Baluta <daniel.baluta@nxp.com>
Acked-by: NNicolin Chen <nicoleotsuka@gmail.com>
Link: https://lore.kernel.org/r/20190806151214.6783-3-daniel.baluta@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>