1. 15 8月, 2016 1 次提交
  2. 11 8月, 2016 1 次提交
    • V
      drm/i915: Rewrite fb rotation GTT handling · 6687c906
      Ville Syrjälä 提交于
      Redo the fb rotation handling in order to:
      - eliminate the NV12 special casing
      - handle fb->offsets[] properly
      - make the rotation handling easier for the plane code
      
      To achieve these goals we reduce intel_rotation_info to only contain
      (for each plane) the rotated view width,height,stride in tile units,
      and the page offset into the object where the plane starts. Each plane
      is handled exactly the same way, no special casing for NV12 or other
      formats. We then store the computed rotation_info under
      intel_framebuffer so that we don't have to recompute it again.
      
      To handle fb->offsets[] we treat them as a linear offsets and convert
      them to x/y offsets from the start of the relevant GTT mapping (either
      normal or rotated). We store the x/y offsets under intel_framebuffer,
      and for some extra convenience we also store the rotated pitch (ie.
      tile aligned plane height). So for each plane we have the normal
      x/y offsets, rotated x/y offsets, and the rotated pitch. The normal
      pitch is available already in fb->pitches[].
      
      While we're gathering up all that extra information, we can also easily
      compute the storage requirements for the framebuffer, so that we can
      check that the object is big enough to hold it.
      
      When it comes time to deal with the plane source coordinates, we first
      rotate the clipped src coordinates to match the relevant GTT view
      orientation, then add to them the fb x/y offsets. Next we compute
      the aligned surface page offset, and as a result we're left with some
      residual x/y offsets. Finally, if required by the hardware, we convert
      the remaining x/y offsets into a linear offset.
      
      For gen2/3 we simply skip computing the final page offset, and just
      convert the src+fb x/y offsets directly into a linear offset since
      that's what the hardware wants.
      
      After this all platforms, incluing SKL+, compute these things in exactly
      the same way (excluding alignemnt differences).
      
      v2: Use BIT(DRM_ROTATE_270) instead of ROTATE_270 when rotating
          plane src coordinates
          Drop some spurious changes that got left behind during
          development
      v3: Split out more changes to prep patches (Daniel)
          s/intel_fb->plane[].foo.bar/intel_fb->foo[].bar/ for brevity
          Rename intel_surf_gtt_offset to intel_fb_gtt_offset
          Kill the pointless 'plane' parameter from intel_fb_gtt_offset()
      v4: Fix alignment vs. alignment-1 when calling
          _intel_compute_tile_offset() from intel_fill_fb_info()
          Pass the pitch in tiles in
          stad of pixels to intel_adjust_tile_offset() from intel_fill_fb_info()
          Pass the full width/height of the rotated area to
          drm_rect_rotate() for clarity
          Use u32 for more offsets
      v5: Preserve the upper_32_bits()/lower_32_bits() handling for the
          fb ggtt offset (Sivakumar)
      v6: Rebase due to drm_plane_state src/dst rects
      
      Cc: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: NSivakumar Thulasimani <sivakumar.thulasimani@intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1470821001-25272-2-git-send-email-ville.syrjala@linux.intel.comAcked-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      6687c906
  3. 06 8月, 2016 1 次提交
    • M
      drm/i915: fix aliasing_ppgtt leak · cb7f2760
      Matthew Auld 提交于
      In i915_ggtt_cleanup_hw we need to remember to free aliasing_ppgtt. This
      fixes the following kmemleak message:
      
      unreferenced object 0xffff880213cca000 (size 8192):
        comm "modprobe", pid 1298, jiffies 4294745402 (age 703.930s)
        hex dump (first 32 bytes):
          00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
          00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
        backtrace:
          [<ffffffff817c808e>] kmemleak_alloc+0x4e/0xb0
          [<ffffffff8121f9c2>] kmem_cache_alloc_trace+0x142/0x1d0
          [<ffffffffa06d11ef>] i915_gem_init_ggtt+0x10f/0x210 [i915]
          [<ffffffffa06d71bb>] i915_gem_init+0x5b/0xd0 [i915]
          [<ffffffffa069749a>] i915_driver_load+0x97a/0x1460 [i915]
          [<ffffffffa06a26ef>] i915_pci_probe+0x4f/0x70 [i915]
          [<ffffffff81423015>] local_pci_probe+0x45/0xa0
          [<ffffffff81424463>] pci_device_probe+0x103/0x150
          [<ffffffff81515e6c>] driver_probe_device+0x22c/0x440
          [<ffffffff81516151>] __driver_attach+0xd1/0xf0
          [<ffffffff8151379c>] bus_for_each_dev+0x6c/0xc0
          [<ffffffff8151555e>] driver_attach+0x1e/0x20
          [<ffffffff81514fa3>] bus_add_driver+0x1c3/0x280
          [<ffffffff81516aa0>] driver_register+0x60/0xe0
          [<ffffffff8142297c>] __pci_register_driver+0x4c/0x50
          [<ffffffffa013605b>] 0xffffffffa013605b
      Signed-off-by: NMatthew Auld <matthew.auld@intel.com>
      Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
      Fixes: b18b6bde ("drm/i915/bdw: Free PPGTT struct")
      Cc: stable@vger.kernel.org
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      Link: http://patchwork.freedesktop.org/patch/msgid/1470420280-21417-1-git-send-email-matthew.auld@intel.com
      cb7f2760
  4. 05 8月, 2016 8 次提交
  5. 04 8月, 2016 9 次提交
  6. 03 8月, 2016 5 次提交
  7. 26 7月, 2016 1 次提交
  8. 20 7月, 2016 1 次提交
  9. 08 7月, 2016 1 次提交
  10. 05 7月, 2016 2 次提交
  11. 04 7月, 2016 1 次提交
  12. 27 6月, 2016 1 次提交
  13. 24 6月, 2016 1 次提交
  14. 18 6月, 2016 1 次提交
  15. 13 6月, 2016 1 次提交
  16. 23 5月, 2016 1 次提交
  17. 20 5月, 2016 1 次提交
  18. 14 5月, 2016 2 次提交
  19. 11 5月, 2016 1 次提交