[Why & How]
We should not allocate any DET for the phantom pipes.
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NWayne Lin <wayne.lin@amd.com>
Signed-off-by: NAlvin Lee <Alvin.Lee2@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
When USB4 DP link training failed and fell back to lower link rate,
the time slot calculation uses the verified_link_cap.
And the verified_link_cap was not updated to the new one.
It caused the wrong VC payload time-slot was allocated.

[How]
Updated verified_link_cap with the new one from cur_link_settings
after the LT completes successfully.
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NWayne Lin <wayne.lin@amd.com>
Signed-off-by: NCruise Hung <Cruise.Hung@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
During hot plug of specific 5K tiled display, sometimes both the tiles
are not synchronized resulting in distortion. The reason is that otgs of
both the tiles goes out of sync when otg workaround (dcnxxx_disable_otg_wa)
is applied for bandwidth optimization. The otg workaround reenables otg
but otg synchronization context is not reset and hence dc_trigger_sync()
does not resynchronize otg again.

[How]
Implement reset_sync_context_for_pipe() to reset the otg synchronization
context for the disabled pipe and its slave pipes when otg workaround is
applied.
Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: NWayne Lin <wayne.lin@amd.com>
Signed-off-by: NMeenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Current DCN3.2 logic for finding the dummy P-state index uses the
DCN3.0 DML validation function instead of DCN3.2 DML.

This can result in either unexpected DML VBA values, or unexpected
dummy P-state index to be used.

[How]
Update the dummy P-state logic to use DCN3.2 DML validation function.
Reviewed-by: NAlvin Lee <alvin.lee2@amd.com>
Reviewed-by: NNevenko Stupar <Nevenko.Stupar@amd.com>
Acked-by: NWayne Lin <wayne.lin@amd.com>
Signed-off-by: NGeorge Shen <george.shen@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
Expose few dchubbun functions in dcn31 and dcn32 to leverage.
Reviewed-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: NWayne Lin <wayne.lin@amd.com>
Signed-off-by: NCharlene Liu <Charlene.Liu@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[WHY]
New dcn301 has 2 less phys
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Acked-by: NWayne Lin <wayne.lin@amd.com>
Signed-off-by: NPavle Kotarac <Pavle.Kotarac@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[WHY]
Adding new asic id for dcn301
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Acked-by: NWayne Lin <wayne.lin@amd.com>
Signed-off-by: NPavle Kotarac <Pavle.Kotarac@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Hostvm should be enabled/disabled accordding to
the status of riommu_active, but hostvm always
be disabled on DCN31 which causes underflow

[How]
Set correct hostvm flag on DCN31
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Acked-by: NWayne Lin <wayne.lin@amd.com>
Signed-off-by: NSherry Wang <Yao.Wang1@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
The urgent latency override is useful when debugging issues
relating to underflow.

Current overridden variable is not correct and has no effect
on DCN3.2 and DCN3.21 DML calculations.

[How]
For DCN3.2 and DCN3.21, override the correct urgent latency
variable when bounding box override is present.
Reviewed-by: NAlvin Lee <alvin.lee2@amd.com>
Reviewed-by: NNevenko Stupar <Nevenko.Stupar@amd.com>
Acked-by: NWayne Lin <wayne.lin@amd.com>
Signed-off-by: NGeorge Shen <george.shen@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why & How]
Uncomment SubVP pipe split assignment in driver since FW headers
are now promoted
Reviewed-by: NMartin Leung <Martin.Leung@amd.com>
Acked-by: NWayne Lin <wayne.lin@amd.com>
Signed-off-by: NAlvin Lee <Alvin.Lee2@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
We have minimal pipe split transition method to avoid pipe
allocation outage.However, this method will invoke audio setup
which cause audio output stuck once pipe reallocate.

[how]
skip audio setup for pipelines which audio stream has been enabled
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Acked-by: NWayne Lin <wayne.lin@amd.com>
Signed-off-by: Nzhikzhai <zhikai.zhai@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
The desktop plane and full-screen game plane may have different
gamut remap coefficients, if switching between desktop and
full-screen game without updating the gamut remap will cause
incorrect color.

[How]
Update gamut remap if planes change.
Reviewed-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: NWayne Lin <wayne.lin@amd.com>
Signed-off-by: NHugo Hu <hugo.hu@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why & How]
Move extra panel power sequencer settings into panel_cofig struct.
Reviewed-by: NAnthony Koo <Anthony.Koo@amd.com>
Acked-by: NWayne Lin <wayne.lin@amd.com>
Signed-off-by: NIan Chen <ian.chen@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This version brings along following fixes:
- Port DCN30 420 logic to DCN32
- Remove some unused definitions from DCN32/321
- Remove dp dig pixle rate div policy from dcn314
- Fix dcn315 reading of memory channel count and width

- Fix SubVP and ODM relevant issues
- Fix pipe split, MPO and ODM relevant issues
- Support proper mst payload removal when link is not in mst mode in dc
- Assume an LTTPR is always present on fixed_vs links
- Rework recent update PHY state commit
- Add debug option and logs
Acked-by: NWayne Lin <wayne.lin@amd.com>
Signed-off-by: NAric Cyr <aric.cyr@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

- Handle pipe split case for SubVP:
  Pass in pipe split index for main and phantom pipes
Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NWayne Lin <wayne.lin@amd.com>
Signed-off-by: NAnthony Koo <Anthony.Koo@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why and How]
- Don't skip bottom and next odm pipe when calculating
  num ways for subvp
- Don't need to double cache lines for DCC (divide by 256)
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NWayne Lin <wayne.lin@amd.com>
Signed-off-by: NAlvin Lee <Alvin.Lee2@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why and How]
- For driver disable cases in current implementation, if P-State
  is unsupported or still supported by firmware, we force it
  supported by DCN.

- SubVP now needs to be included in this case along with FPO.
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NWayne Lin <wayne.lin@amd.com>
Signed-off-by: NAlvin Lee <Alvin.Lee2@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why and How]
For SubVP pipe split case, pass in split index for
main and phantom pipes to ensure that the P-State
sequence will force P-State for all required pipes.
Reviewed-by: NNevenko Stupar <Nevenko.Stupar@amd.com>
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NWayne Lin <wayne.lin@amd.com>
Signed-off-by: NAlvin Lee <Alvin.Lee2@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why and How]
- Add a debug option for allocating extra way for cursor
- Remove usage of cache_cursor_addr since it's not gaurenteed
  to be populated
- Include cursor size in MALL calculation if it exceeds the
  DCN cursor buffer size (and don't need extra way for cursor)
Reviewed-by: NAurabindo Pillai <Aurabindo.Pillai@amd.com>
Acked-by: NWayne Lin <wayne.lin@amd.com>
Signed-off-by: NAlvin Lee <Alvin.Lee2@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why & How]
ODM seamless transitions require DIV_MODE_AUTO. However,
DIV_MODE_AUTO only works when all the horizontal timing params
are divisible by the ODM combine factor. Therefore, disable the
ODM 2:1 policy when the horizontal timing params are not divisible
by 2.
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NWayne Lin <wayne.lin@amd.com>
Signed-off-by: NAlvin Lee <Alvin.Lee2@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
When user unplugs mst hubs, the current code will forcefully zero
entire mst payload allocation table structure stored in link before we
deallocate actual payload when disabling stream.

During the first disable stream sequence, we will use current mst
payload allocation table to determine if link should be turned off.
Because we zero out it before we are disabling stream, the payload
allocation table stored in link doesn't represent the actual allocation status,
so we turn off link at the first disable stream without waiting until all
streams' payloads have been deallocated. This avoilates the designed
deallocation sequence and caused system hang in DP2 scenario.

[how]
Remove payload during deallocation and never zero payload allocation structure
without actually deallocating payload.
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NWayne Lin <wayne.lin@amd.com>
Signed-off-by: NWenjing Liu <wenjing.liu@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
Original change 594b237b ("drm/amd/display: Add
interface to track PHY state") was implemented by assuming stream's
dpms off is equivalent to PHY power off.
This assumption doesn't hold in following situations:
1. MST multiple stream scenario, where multiple streams are sharing the
same PHY output. Toggle dpms off for one of the stream doesn't power
off the PHY due to the presence of other streams.
2. enable stream failure scenario, where enable stream fails due to
failure of link training. This will cause DPMS off is set to false, while
the actual PHY power state is off in certain cases.
Due to the problematic assumption, the logic will skip disabling
other streams for MST multiple stream scenario, therefore PHY is
not actually powered off.

[how]
1. Rework this refactor by moving PHY state update down to hardware
level, where we update PHY state in place when hardware sequencer
is actually changing the power state of the PHY hardware.
2. Reimplement symclk on TX off workaround in place when we are actually
calling transmitter control to power off PHY in dcn32. Note the workaround is
added due to the lack of proper software interface to set TX while keeping
symclk on. We plan to address this interface problem so we can set TX off
only without affecting symclk in future dcn versions.

Fixes: 594b237b ("drm/amd/display: Add interface to track PHY state")
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NWayne Lin <wayne.lin@amd.com>
Signed-off-by: NWenjing Liu <wenjing.liu@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This patch addes MES and MES-KIQ version in debugfs.
Signed-off-by: NYifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: NTim Huang <Tim.Huang@amd.com>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[WHY]
LTTPRs can in very rare instsances fail to increment DPCD LTTPR count.
This results in aux-i LTTPR requests to be sent to the wrong DPCD
address, which causes link training failure.

[HOW]
Override internal repeater count if fixed_vs flag is set for a given link
Reviewed-by: NGeorge Shen <George.Shen@amd.com>
Acked-by: NWayne Lin <wayne.lin@amd.com>
Signed-off-by: NMichael Strauss <michael.strauss@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why & How]
Correctly set ddr5 channel width to 8 bytes
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NWayne Lin <wayne.lin@amd.com>
Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]

DC makes use of layer_index (zpos) when picking the HW plane to enable
HW cursor on. However, some compositors will not attach zpos information
to each DRM plane. Consequently, in amdgpu, we default layer_index to 0
and do not update it.

This causes said DC logic to enable HW cursor on all planes of the same
layer_index, which manifests as a double cursor issue if one of the
planes is scaled (and hence scaling the cursor as well).

[How]

Use DRM core helpers to calculate a normalized_zpos value for each
drm_plane_state under each crtc, within the atomic state.

This helper will first consider existing zpos values, and if
identical/unset, fallback to plane ID ordering.

The normalized_zpos is then passed to dc_plane_info during atomic check
for later use by the cursor logic.
Reviewed-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: NWayne Lin <wayne.lin@amd.com>
Signed-off-by: NLeo Li <sunpeng.li@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why and How]
- Only consider pixel rate div policy for DCN32+
Reviewed-by: NMartin Leung <Martin.Leung@amd.com>
Acked-by: NWayne Lin <wayne.lin@amd.com>
Signed-off-by: NAlvin Lee <Alvin.Lee2@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why & How]
Added logs for panel delays, spread_spectrum_percentage,
and gpuclk_ss_percentage to facilitate debugging.
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Acked-by: NWayne Lin <wayne.lin@amd.com>
Signed-off-by: NLeo Chen <sancchen@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why & How]
Support dramclk change latency change via debug option and add some
code isolation.
Reviewed-by: NMartin Leung <Martin.Leung@amd.com>
Acked-by: NWayne Lin <wayne.lin@amd.com>
Signed-off-by: NCharlene Liu <Charlene.Liu@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why & How]
- Pipe split prediction previously only took into
account MPC split. We must also consider when
ODM combine is required, and when we apply ODM
combine by policy.

- Also re-work DET allocation function as it wasn't
properly splitting the DET per stream, per plane.
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NWayne Lin <wayne.lin@amd.com>
Signed-off-by: NAlvin Lee <Alvin.Lee2@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why&How]
After reg offset initialization was switched to runtime rather than
compile time, some of the defintions are not needed anymore and can
be removed.
Acked-by: NWayne Lin <wayne.lin@amd.com>
Signed-off-by: NAurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
420 modes are limited by FMT buffer width of 4096
which requires multi-pipe support in form of ODM
combine.  If 420 modes have greater HActive than
4096, the DML logic should accomodate whether
it should be rejected, or ODM combine 2:1 or 4:1
is triggered accordingly.

[How]
FMT Buffer limit of 4096 in DCN32. Force ODM
combine depending on HActive and FMT Buffer limit.
Reject modes if TMDS 420 and above 4096.
Acked-by: NWayne Lin <wayne.lin@amd.com>
Signed-off-by: NChris Park <chris.park@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

clean up some inconsistent indentings

Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2182Reported-by: NAbaci Robot <abaci@linux.alibaba.com>
Signed-off-by: NYang Li <yang.lee@linux.alibaba.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

clean up some inconsistent indentings

Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2181Reported-by: NAbaci Robot <abaci@linux.alibaba.com>
Signed-off-by: NYang Li <yang.lee@linux.alibaba.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

clean up some inconsistent indentings

Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2180Reported-by: NAbaci Robot <abaci@linux.alibaba.com>
Signed-off-by: NYang Li <yang.lee@linux.alibaba.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

clean up some inconsistent indentings

Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2179Reported-by: NAbaci Robot <abaci@linux.alibaba.com>
Signed-off-by: NYang Li <yang.lee@linux.alibaba.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

clean up some inconsistent indentings

Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2178Reported-by: NAbaci Robot <abaci@linux.alibaba.com>
Signed-off-by: NYang Li <yang.lee@linux.alibaba.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

clean up some inconsistent indentings

Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2177Reported-by: NAbaci Robot <abaci@linux.alibaba.com>
Signed-off-by: NYang Li <yang.lee@linux.alibaba.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

There is a spelling mistake in a pr_debug message. Fix it.
Signed-off-by: NColin Ian King <colin.i.king@gmail.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

amdgpu_firmware_info debugfs will show rlcv/rlcp
ucode version info
Signed-off-by: NHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: NLikun Gao <Likun.Gao@amd.com>
Reviewed-by: NFeifei Xu <Feifei.Xu@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>