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  1. 10 9月, 2009 2 次提交
  3. 09 9月, 2009 34 次提交
  5. 07 9月, 2009 4 次提交
    • D
      r8169: Fix warning in rtl8169_start_xmit(). · 3a5f29c1
      由 David S. Miller 提交于 
      Reported by Stephen Rothwell:

drivers/net/r8169.c: In function 'rtl8169_start_xmit':
drivers/net/r8169.c:3421: warning: label 'out' defined but not used

Introduced by commit 61357325 ("netdev:
convert bulk of drivers to netdev_tx_t").
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      3a5f29c1
    • R
      net: fix hydra printk format warning · cf33ce15
      由 Randy Dunlap 提交于 
      m68k:
drivers/net/hydra.c:178: warning: format '%08lx' expects type 'long unsigned int', but argument 3 has type 'resource_size_t'
Signed-off-by: NRandy Dunlap <randy.dunlap@oracle.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      cf33ce15
    • K
      IXP42x HSS support for setting internal clock rate · 5dbc4650
      由 Krzysztof Halasa 提交于 
      HSS usually uses external clocks, so it's not a big deal. Internal clock
is used for direct DTE-DTE connections and when the DCE doesn't provide
it's own clock.

This also depends on the oscillator frequency. Intel seems to have
calculated the clock register settings for 33.33 MHz (66.66 MHz timer
base). Their settings seem quite suboptimal both in terms of average
frequency (60 ppm is unacceptable for G.703 applications, their primary
intended usage(?)) and jitter.

Many (most?) platforms use a 33.333 MHz oscillator, a 10 ppm difference
from Intel's base.

Instead of creating static tables, I've created a procedure to program
the HSS clock register. The register consists of 3 parts (A, B, C).
The average frequency (= bit rate) is:
66.66x MHz / (A  + (B + 1) / (C + 1))
The procedure aims at the closest average frequency, possibly at the
cost of increased jitter. Nobody would be able to directly drive an
unbufferred transmitter with a HSS anyway, and the frequency error is
what it really counts.

I've verified the above with an oscilloscope on IXP425. It seems IXP46x
and possibly IXP43x use a bit different clock generation algorithm - it
looks like the avg frequency is:
(on IXP465) 66.66x MHz / (A  + B / (C + 1)).
Also they use much greater precomputed A and B - on IXP425 it would
simply result in more jitter, but I don't know how does it work on
IXP46x (perhaps 3 least significant bits aren't used?).

Anyway it looks that they were aiming for exactly +60 ppm or -60 ppm,
while <1 ppm is typically possible (with a synchronized clock, of
course).

The attached patch makes it possible to set almost any bit rate
(my IXP425 533 MHz quits at > 22 Mb/s if a single port is used, and the
minimum is ca. 65 Kb/s).

This is independent of MVIP (multi-E1/T1 on one HSS) mode.
Signed-off-by: NKrzysztof Hałasa <khc@pm.waw.pl>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      5dbc4650
    • K
      WAN: remove deprecated PCI_DEVICE_ID from PCI200SYN driver. · 32e6a0c8
      由 Krzysztof Halasa 提交于 
      PCI200SYN has its own PCI subsystem device ID for 3+ years, now it's
time to remove the generic PLX905[02] ID from the driver. Anyone with
old EEPROM data will have to run the upgrade.

Having the generic PLX905[02] (PCI-local bus bridge) ID is harmful
as the driver tries to handle other devices based on these bridges.
Signed-off-by: NKrzysztof Halasa <khc@pm.waw.pl>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      32e6a0c8