- 22 11月, 2019 1 次提交
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由 Konstantin Khlebnikov 提交于
Requests that triggers flushing volatile writeback cache to disk (barriers) have significant effect to overall performance. Block layer has sophisticated engine for combining several flush requests into one. But there is no statistics for actual flushes executed by disk. Requests which trigger flushes usually are barriers - zero-size writes. This patch adds two iostat counters into /sys/class/block/$dev/stat and /proc/diskstats - count of completed flush requests and their total time. Signed-off-by: NKonstantin Khlebnikov <khlebnikov@yandex-team.ru> Signed-off-by: NJens Axboe <axboe@kernel.dk>
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- 16 11月, 2019 1 次提交
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由 Mikulas Patocka 提交于
Metadata runs are supposed to be aligned on 4k boundary (so that they work efficiently with disks with 4k sectors). However, there was a programming bug that makes them aligned on 128k boundary instead. The unused space is wasted. Fix this bug by providing a proper 4k alignment. In order to keep existing volumes working, we introduce a new flag SB_FLAG_FIXED_PADDING - when the flag is clear, we calculate the padding the old way. In order to make sure that the old version cannot mount the volume created by the new version, we increase superblock version to 4. Also in order to not break with old integritysetup, we fix alignment only if the parameter "fix_padding" is present when formatting the device. Signed-off-by: NMikulas Patocka <mpatocka@redhat.com> Signed-off-by: NMike Snitzer <snitzer@redhat.com>
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- 14 11月, 2019 2 次提交
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由 Eric Biggers 提交于
Document that the statx() system call can now be used to check whether a file is a verity file. Signed-off-by: NEric Biggers <ebiggers@google.com>
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由 Eric Biggers 提交于
I had meant to replace these TODOs with the actual version when applying the patches, but forgot to do so. Do it now. Signed-off-by: NEric Biggers <ebiggers@google.com>
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- 13 11月, 2019 1 次提交
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由 Andrey Pronin 提交于
Add TPM2.0 PTP FIFO compatible SPI interface for chips with Cr50 firmware. Cc: Andrey Pronin <apronin@chromium.org> Cc: Duncan Laurie <dlaurie@chromium.org> Cc: Jason Gunthorpe <jgg@ziepe.ca> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Guenter Roeck <groeck@chromium.org> Cc: Alexander Steffen <Alexander.Steffen@infineon.com> Cc: Heiko Stuebner <heiko@sntech.de> Signed-off-by: NAndrey Pronin <apronin@chromium.org> Reviewed-by: NRob Herring <robh@kernel.org> Signed-off-by: NStephen Boyd <swboyd@chromium.org> Acked-by: NJarkko Sakkinen <jarkko.sakkinen@linux.intel.com> Signed-off-by: NJarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
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- 07 11月, 2019 1 次提交
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由 Eric Biggers 提交于
Inline encryption hardware compliant with the UFS v2.1 standard or with the upcoming version of the eMMC standard has the following properties: (1) Per I/O request, the encryption key is specified by a previously loaded keyslot. There might be only a small number of keyslots. (2) Per I/O request, the starting IV is specified by a 64-bit "data unit number" (DUN). IV bits 64-127 are assumed to be 0. The hardware automatically increments the DUN for each "data unit" of configurable size in the request, e.g. for each filesystem block. Property (1) makes it inefficient to use the traditional fscrypt per-file keys. Property (2) precludes the use of the existing DIRECT_KEY fscrypt policy flag, which needs at least 192 IV bits. Therefore, add a new fscrypt policy flag IV_INO_LBLK_64 which causes the encryption to modified as follows: - The encryption keys are derived from the master key, encryption mode number, and filesystem UUID. - The IVs are chosen as (inode_number << 32) | file_logical_block_num. For filenames encryption, file_logical_block_num is 0. Since the file nonces aren't used in the key derivation, many files may share the same encryption key. This is much more efficient on the target hardware. Including the inode number in the IVs and mixing the filesystem UUID into the keys ensures that data in different files is nevertheless still encrypted differently. Additionally, limiting the inode and block numbers to 32 bits and placing the block number in the low bits maintains compatibility with the 64-bit DUN convention (property (2) above). Since this scheme assumes that inode numbers are stable (which may preclude filesystem shrinking) and that inode and file logical block numbers are at most 32-bit, IV_INO_LBLK_64 will only be allowed on filesystems that meet these constraints. These are acceptable limitations for the cases where this format would actually be used. Note that IV_INO_LBLK_64 is an on-disk format, not an implementation. This patch just adds support for it using the existing filesystem layer encryption. A later patch will add support for inline encryption. Reviewed-by: NPaul Crowley <paulcrowley@google.com> Co-developed-by: NSatya Tangirala <satyat@google.com> Signed-off-by: NSatya Tangirala <satyat@google.com> Signed-off-by: NEric Biggers <ebiggers@google.com>
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- 06 11月, 2019 2 次提交
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由 Tariq Toukan 提交于
Add TLS TX counter description for the handshake retransmitted packets that triggers the resync procedure then skip it, going into the regular transmit flow. Fixes: 46a3ea98 ("net/mlx5e: kTLS, Enhance TX resync flow") Signed-off-by: NTariq Toukan <tariqt@mellanox.com> Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com> Acked-by: NJakub Kicinski <jakub.kicinski@netronome.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Heinz Mauelshagen 提交于
This fixes a flaw causing raid set extensions not to be synchronized in case the MD bitmap resize required additional pages to be allocated. Also share resize code in the raid constructor between new size changes and those occuring during recovery. Bump the target version to define the change and document it in Documentation/admin-guide/device-mapper/dm-raid.rst. Reported-by: NSteve D <steved424@gmail.com> Signed-off-by: NHeinz Mauelshagen <heinzm@redhat.com> Signed-off-by: NMike Snitzer <snitzer@redhat.com>
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- 05 11月, 2019 5 次提交
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由 Gomez Iglesias, Antonio 提交于
Add the initial ITLB_MULTIHIT documentation. [ tglx: Add it to the index so it gets actually built. ] Signed-off-by: NAntonio Gomez Iglesias <antonio.gomez.iglesias@intel.com> Signed-off-by: NNelson D'Souza <nelson.dsouza@linux.intel.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com> Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
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由 Junaid Shahid 提交于
The page table pages corresponding to broken down large pages are zapped in FIFO order, so that the large page can potentially be recovered, if it is not longer being used for execution. This removes the performance penalty for walking deeper EPT page tables. By default, one large page will last about one hour once the guest reaches a steady state. Signed-off-by: NJunaid Shahid <junaids@google.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com> Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
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由 Joakim Zhang 提交于
Add capabilities information for AXI ID filter. Signed-off-by: NJoakim Zhang <qiangqing.zhang@nxp.com> Signed-off-by: NWill Deacon <will@kernel.org>
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由 Joakim Zhang 提交于
Add new compatible string for i.MX8MPlus DDR PMU core. Signed-off-by: NJoakim Zhang <qiangqing.zhang@nxp.com> Signed-off-by: NWill Deacon <will@kernel.org>
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由 Joakim Zhang 提交于
Add explanation for DDR_CAP_AXI_ID_FILTER_ENHANCED quirk. Signed-off-by: NJoakim Zhang <qiangqing.zhang@nxp.com> [will: Simplified wording] Signed-off-by: NWill Deacon <will@kernel.org>
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- 04 11月, 2019 2 次提交
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由 Paolo Bonzini 提交于
With some Intel processors, putting the same virtual address in the TLB as both a 4 KiB and 2 MiB page can confuse the instruction fetch unit and cause the processor to issue a machine check resulting in a CPU lockup. Unfortunately when EPT page tables use huge pages, it is possible for a malicious guest to cause this situation. Add a knob to mark huge pages as non-executable. When the nx_huge_pages parameter is enabled (and we are using EPT), all huge pages are marked as NX. If the guest attempts to execute in one of those pages, the page is broken down into 4K pages, which are then marked executable. This is not an issue for shadow paging (except nested EPT), because then the host is in control of TLB flushes and the problematic situation cannot happen. With nested EPT, again the nested guest can cause problems shadow and direct EPT is treated in the same way. [ tglx: Fixup default to auto and massage wording a bit ] Originally-by: NJunaid Shahid <junaids@google.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com> Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
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由 Vineela Tummalapalli 提交于
Some processors may incur a machine check error possibly resulting in an unrecoverable CPU lockup when an instruction fetch encounters a TLB multi-hit in the instruction TLB. This can occur when the page size is changed along with either the physical address or cache type. The relevant erratum can be found here: https://bugzilla.kernel.org/show_bug.cgi?id=205195 There are other processors affected for which the erratum does not fully disclose the impact. This issue affects both bare-metal x86 page tables and EPT. It can be mitigated by either eliminating the use of large pages or by using careful TLB invalidations when changing the page size in the page tables. Just like Spectre, Meltdown, L1TF and MDS, a new bit has been allocated in MSR_IA32_ARCH_CAPABILITIES (PSCHANGE_MC_NO) and will be set on CPUs which are mitigated against this issue. Signed-off-by: NVineela Tummalapalli <vineela.tummalapalli@intel.com> Co-developed-by: NPawan Gupta <pawan.kumar.gupta@linux.intel.com> Signed-off-by: NPawan Gupta <pawan.kumar.gupta@linux.intel.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com> Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
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- 02 11月, 2019 1 次提交
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由 Jonathan Neuschäfer 提交于
These asterisks were once references to a line that said: "* Other names and brands may be claimed as the property of others." But now, they serve no purpose; they can only irritate the reader. Fixes: de3edab4 ("e1000: update README for e1000") Fixes: a3fb6568 ("e100.txt: Cleanup license info in kernel doc") Fixes: da8c01c4 ("e1000e.txt: Add e1000e documentation") Fixes: f12a84a9 ("Documentation: fm10k: Add kernel documentation") Fixes: b55c52b1 ("igb.txt: Add igb documentation") Fixes: c4e9b56e ("igbvf.txt: Add igbvf Documentation") Fixes: d7064f4c ("Documentation/networking/: Update Intel wired LAN driver documentation") Fixes: c4b8c011 ("ixgbevf.txt: Update ixgbevf documentation") Fixes: 1e06edcc ("Documentation: i40e: Prepare documentation for RST conversion") Fixes: 105bf2fe ("i40evf: add driver to kernel build system") Fixes: 1fae869b ("Documentation: ice: Prepare documentation for RST conversion") Fixes: df69ba43 ("ionic: Add basic framework for IONIC Network device driver") Signed-off-by: NJonathan Neuschäfer <j.neuschaefer@gmx.net> Tested-by: NAaron Brown <aaron.f.brown@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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- 01 11月, 2019 7 次提交
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由 Julien Grall 提交于
Commit "docs/arm64: cpu-feature-registers: Documents missing visible fields" added bitfields following the convention [s, e]. However, the documentation is following [s, e] and so does the Arm ARM. Rewrite the bitfields to match the format [s, e]. Fixes: a8613e70 ("docs/arm64: cpu-feature-registers: Documents missing visible fields") Signed-off-by: NJulien Grall <julien.grall@arm.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Jiri Slaby 提交于
In case a driver wants to return an error from qc_prep, return enum ata_completion_errors. sata_mv is one of those drivers -- see the next patch. Other drivers return the newly defined AC_ERR_OK. [v2] use enum ata_completion_errors and AC_ERR_OK. Signed-off-by: NJiri Slaby <jslaby@suse.cz> Cc: Jens Axboe <axboe@kernel.dk> Cc: linux-ide@vger.kernel.org Signed-off-by: NJens Axboe <axboe@kernel.dk>
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由 Jiri Slaby 提交于
ata_qc_prep no longer exists, there are ata_bmdma_qc_prep and ata_bmdma_dumb_qc_prep instead. And most drivers do not use them, so reword the paragraph. ata_qc_issue_prot was renamed to ata_sff_qc_issue. ->tf_load is now ->sff_tf_load. Fix them. And fix spelling supercede -> supersede. Signed-off-by: NJiri Slaby <jslaby@suse.cz> Cc: Jens Axboe <axboe@kernel.dk> Cc: linux-ide@vger.kernel.org Signed-off-by: NJens Axboe <axboe@kernel.dk>
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由 Florian Fainelli 提交于
The Broadcom Brahma-B53 core is susceptible to the issue described by ARM64_ERRATUM_843419 so this commit enables the workaround to be applied when executing on that core. Since there are now multiple entries to match, we must convert the existing ARM64_ERRATUM_843419 into an erratum list and use cpucap_multi_entry_cap_matches to match our entries. Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NWill Deacon <will@kernel.org>
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由 Doug Berger 提交于
The Broadcom Brahma-B53 core is susceptible to the issue described by ARM64_ERRATUM_845719 so this commit enables the workaround to be applied when executing on that core. Since there are now multiple entries to match, we must convert the existing ARM64_ERRATUM_845719 into an erratum list. Signed-off-by: NDoug Berger <opendmb@gmail.com> Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NWill Deacon <will@kernel.org>
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由 Eric Dumazet 提交于
tcp_max_syn_backlog default value depends on memory size and TCP ehash size. Before this patch, the max value was 2048 [1], which is considered too small nowadays. Increase it to 4096 to match the recent SOMAXCONN change. [1] This is with TCP ehash size being capped to 524288 buckets. Signed-off-by: NEric Dumazet <edumazet@google.com> Cc: Willy Tarreau <w@1wt.eu> Cc: Yue Cao <ycao009@ucr.edu> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Eric Dumazet 提交于
SOMAXCONN is /proc/sys/net/core/somaxconn default value. It has been defined as 128 more than 20 years ago. Since it caps the listen() backlog values, the very small value has caused numerous problems over the years, and many people had to raise it on their hosts after beeing hit by problems. Google has been using 1024 for at least 15 years, and we increased this to 4096 after TCP listener rework has been completed, more than 4 years ago. We got no complain of this change breaking any legacy application. Many applications indeed setup a TCP listener with listen(fd, -1); meaning they let the system select the backlog. Raising SOMAXCONN lowers chance of the port being unavailable under even small SYNFLOOD attack, and reduces possibilities of side channel vulnerabilities. Signed-off-by: NEric Dumazet <edumazet@google.com> Cc: Willy Tarreau <w@1wt.eu> Cc: Yue Cao <ycao009@ucr.edu> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 31 10月, 2019 1 次提交
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由 Bjorn Andersson 提交于
The Kryo cores share errata 1009 with Falkor, so add their model definitions and enable it for them as well. Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org> [will: Update entry in silicon-errata.rst] Signed-off-by: NWill Deacon <will@kernel.org>
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- 29 10月, 2019 2 次提交
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由 Linus Walleij 提交于
This adds device tree bindings for the Intel IXP4xx flash controller, a simple physmap which however need a specific big-endian or mixed-endian access pattern to the memory. Cc: devicetree@vger.kernel.org Reviewed-by: NRob Herring <robh@kernel.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>
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Add documentation for Cavium Coherent Processor Interconnect (CCPI2) PMU. Signed-off-by: NGanapatrao Prabhakerrao Kulkarni <gkulkarni@marvell.com> Signed-off-by: NWill Deacon <will@kernel.org>
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- 28 10月, 2019 4 次提交
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由 Marek Bykowski 提交于
Indicate the arm-ccn perf back-end supports now ccn-512. Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NMarek Bykowski <marek.bykowski@gmail.com> Signed-off-by: NWill Deacon <will@kernel.org>
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由 Pawan Gupta 提交于
Add the documenation for TSX Async Abort. Include the description of the issue, how to check the mitigation state, control the mitigation, guidance for system administrators. [ bp: Add proper SPDX tags, touch ups by Josh and me. ] Co-developed-by: NAntonio Gomez Iglesias <antonio.gomez.iglesias@intel.com> Signed-off-by: NPawan Gupta <pawan.kumar.gupta@linux.intel.com> Signed-off-by: NAntonio Gomez Iglesias <antonio.gomez.iglesias@intel.com> Signed-off-by: NBorislav Petkov <bp@suse.de> Signed-off-by: NThomas Gleixner <tglx@linutronix.de> Reviewed-by: NMark Gross <mgross@linux.intel.com> Reviewed-by: NTony Luck <tony.luck@intel.com> Reviewed-by: NJosh Poimboeuf <jpoimboe@redhat.com>
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由 Pawan Gupta 提交于
Platforms which are not affected by X86_BUG_TAA may want the TSX feature enabled. Add "auto" option to the TSX cmdline parameter. When tsx=auto disable TSX when X86_BUG_TAA is present, otherwise enable TSX. More details on X86_BUG_TAA can be found here: https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html [ bp: Extend the arg buffer to accommodate "auto\0". ] Signed-off-by: NPawan Gupta <pawan.kumar.gupta@linux.intel.com> Signed-off-by: NBorislav Petkov <bp@suse.de> Signed-off-by: NThomas Gleixner <tglx@linutronix.de> Reviewed-by: NTony Luck <tony.luck@intel.com> Reviewed-by: NJosh Poimboeuf <jpoimboe@redhat.com>
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由 Pawan Gupta 提交于
Add a kernel cmdline parameter "tsx" to control the Transactional Synchronization Extensions (TSX) feature. On CPUs that support TSX control, use "tsx=on|off" to enable or disable TSX. Not specifying this option is equivalent to "tsx=off". This is because on certain processors TSX may be used as a part of a speculative side channel attack. Carve out the TSX controlling functionality into a separate compilation unit because TSX is a CPU feature while the TSX async abort control machinery will go to cpu/bugs.c. [ bp: - Massage, shorten and clear the arg buffer. - Clarifications of the tsx= possible options - Josh. - Expand on TSX_CTRL availability - Pawan. ] Signed-off-by: NPawan Gupta <pawan.kumar.gupta@linux.intel.com> Signed-off-by: NBorislav Petkov <bp@suse.de> Signed-off-by: NThomas Gleixner <tglx@linutronix.de> Reviewed-by: NJosh Poimboeuf <jpoimboe@redhat.com>
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- 26 10月, 2019 2 次提交
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由 Marc Zyngier 提交于
Now that everything is in place, let's get the ball rolling by allowing the corresponding config option to be selected. Also add the required information to silicon_errata.rst. Acked-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NMarc Zyngier <maz@kernel.org>
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由 James Morse 提交于
Cores affected by Neoverse-N1 #1542419 could execute a stale instruction when a branch is updated to point to freshly generated instructions. To workaround this issue we need user-space to issue unnecessary icache maintenance that we can trap. Start by hiding CTR_EL0.DIC. Reviewed-by: NSuzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: NJames Morse <james.morse@arm.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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- 25 10月, 2019 1 次提交
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由 Dave Martin 提交于
Commit d71be2b6 ("arm64: cpufeature: Detect SSBS and advertise to userspace") exposes ID_AA64PFR1_EL1 to userspace, but didn't update the documentation to match. Add it. Acked-by: NWill Deacon <will@kernel.org> Signed-off-by: NDave Martin <Dave.Martin@arm.com> Signed-off-by: NMark Brown <broonie@kernel.org> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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- 24 10月, 2019 1 次提交
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由 Rob Herring 提交于
Fix the errors in the RiscV CPU DT schema: Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: 'timebase-frequency' is a required property Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@1: 'timebase-frequency' is a required property Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: compatible:0: 'riscv' is not one of ['sifive,rocket0', 'sifive,e5', 'sifive,e51', 'sifive,u54-mc', 'sifive,u54', 'sifive,u5'] Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: compatible: ['riscv'] is too short Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: 'timebase-frequency' is a required property The DT spec allows for 'timebase-frequency' to be in 'cpu' or 'cpus' node and RiscV requires it in /cpus node, so make it disallowed in cpu nodes. Fixes: 4fd669a8 ("dt-bindings: riscv: convert cpu binding to json-schema") Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: linux-riscv@lists.infradead.org Acked-by: NPaul Walmsley <paul.walmsley@sifive.com> Signed-off-by: NRob Herring <robh@kernel.org>
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- 22 10月, 2019 2 次提交
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由 Eric Biggers 提交于
The 'f' ioctls with numbers 19-26 decimal are currently used for fscrypt (a.k.a. ext4/f2fs/ubifs encryption), and up to 39 decimal is reserved for future fscrypt use, as per the comment in fs/ext4/ext4.h. So the reserved range is 13-27 hex. Document this in ioctl-number.rst. Signed-off-by: NEric Biggers <ebiggers@google.com>
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由 Eric Biggers 提交于
Instead of open-coding the calculations for ESSIV handling, use an ESSIV skcipher which does all of this under the hood. ESSIV was added to the crypto API in v5.4. This is based on a patch from Ard Biesheuvel, but reworked to apply after all the fscrypt changes that went into v5.4. Tested with 'kvm-xfstests -c ext4,f2fs -g encrypt', including the ciphertext verification tests for v1 and v2 encryption policies. Originally-from: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: NArd Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: NEric Biggers <ebiggers@google.com>
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- 16 10月, 2019 1 次提交
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由 Andrew Jeffery 提交于
Rename SD3 functions and groups to EMMC to better reflect their intended use before the binding escapes too far into the wild. Also clean up the SD3 pin groups to eliminate some silliness that slipped through the cracks (SD3DAT[4-7]) by unifying them into three new groups: EMMCG1, EMMCG4 and EMMCG8 for 1, 4 and 8-bit data buses respectively. Signed-off-by: NAndrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191008044153.12734-2-andrew@aj.id.auReviewed-by: NRob Herring <robh@kernel.org> Reviewed-by: NJoel Stanley <joel@jms.id.au> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 15 10月, 2019 2 次提交
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由 Marc Zyngier 提交于
It goes without saying, but better saying it: the kernel expects ICC_CTLR_EL3.PMHE to have the same value across all CPUs, and for that setting not to change during the lifetime of the kernel. Signed-off-by: NMarc Zyngier <maz@kernel.org> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Vlastimil Babka 提交于
Commit 8974558f ("mm, page_owner, debug_pagealloc: save and dump freeing stack trace") enhanced page_owner to also store freeing stack trace, when debug_pagealloc is also enabled. KASAN would also like to do this [1] to improve error reports to debug e.g. UAF issues. Kirill has suggested that the freeing stack trace saving should be also possible to be enabled separately from KASAN or debug_pagealloc, i.e. with an extra boot option. Qian argued that we have enough options already, and avoiding the extra overhead is not worth the complications in the case of a debugging option. Kirill noted that the extra stack handle in struct page_owner requires 0.1% of memory. This patch therefore enables free stack saving whenever page_owner is enabled, regardless of whether debug_pagealloc or KASAN is also enabled. KASAN kernels booted with page_owner=on will thus benefit from the improved error reports. [1] https://bugzilla.kernel.org/show_bug.cgi?id=203967 [vbabka@suse.cz: v3] Link: http://lkml.kernel.org/r/20191007091808.7096-3-vbabka@suse.cz Link: http://lkml.kernel.org/r/20190930122916.14969-3-vbabka@suse.czSigned-off-by: NVlastimil Babka <vbabka@suse.cz> Reviewed-by: NQian Cai <cai@lca.pw> Suggested-by: NDmitry Vyukov <dvyukov@google.com> Suggested-by: NWalter Wu <walter-zh.wu@mediatek.com> Suggested-by: NAndrey Ryabinin <aryabinin@virtuozzo.com> Suggested-by: NKirill A. Shutemov <kirill.shutemov@linux.intel.com> Suggested-by: NQian Cai <cai@lca.pw> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 14 10月, 2019 1 次提交
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由 Julien Grall 提交于
A couple of fields visible to userspace are not described in the documentation. So update it. Acked-by: NWill Deacon <will@kernel.org> Signed-off-by: NJulien Grall <julien.grall@arm.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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