On few SDHCI-MSM controllers, the host controller's clock tuning
circuit may go out of sync if controller clocks are gated which
eventually will result in data CRC, command CRC/timeout errors.
To overcome this h/w limitation, the DLL needs to be re-initialized
and restored with its old settings once clocks are ungated.
Signed-off-by: NVeerabhadrarao Badiganti <vbadigan@codeaurora.org>
Reviewed-by: NEvan Green <evgreen@chromium.org>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

There is a error message within devm_ioremap_resource
already, so remove the dev_err call to avoid redundant
error message.
Signed-off-by: NWei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Add support to use the new compatible string "qcom,sdhci-msm-v5".

Based on the msm variant, pick the relevant variant data and
use it for register read/write to msm specific registers.
Signed-off-by: NSayali Lokhande <sayalil@codeaurora.org>
Signed-off-by: NVijay Viswanath <vviswana@codeaurora.org>
Reviewed-by: NEvan Green <evgreen@chromium.org>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

In addition to offsets of certain registers changing, the registers in
core_mem have been shifted to HC mem as well. To access these
registers, define msm version specific functions. These functions can
be loaded into the function pointers at the time of probe based on
the msm version detected.

Also defind new data structure to hold version specific Ops and
register addresses.
Signed-off-by: NSayali Lokhande <sayalil@codeaurora.org>
Signed-off-by: NVijay Viswanath <vviswana@codeaurora.org>
Reviewed-by: NEvan Green <evgreen@chromium.org>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

For SDCC version 5.0.0, MCI registers are removed from SDCC
interface and some registers are moved to HC.
Define a new data structure where we can statically define
the address offsets for the registers in different SDCC versions.
Signed-off-by: NSayali Lokhande <sayalil@codeaurora.org>
Signed-off-by: NVijay Viswanath <vviswana@codeaurora.org>
Reviewed-by: NEvan Green <evgreen@chromium.org>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Now we have a proper implementation for the power irq handling and this
quirk is not needed anymore. In fact, it is causing card detection delays
on apq8096 platforms and the following error is displayed:
sdhci_msm 74a4900.sdhci: mmc0: pwr_irq for req: (4) timed out

The quirk is forcing the controller to retain 1.8V signalling on the slot
even when a new card is inserted, which is not correct. The proper behavior
would be to reset the controller in order to start with 3.3V signaling.

Fixes: c0309b38 ("mmc: sdhci-msm: Add sdhci msm register write APIs which wait for pwr irq")
Suggested-by: NVijay Viswanath <vviswana@codeaurora.org>
Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

The PADs for SD card are dual-voltage that support 3v/1.8v. Those PADs
have a control signal  (io_pad_pwr_switch/mode18 ) that indicates
whether the PAD works in 3v or 1.8v.

SDHC core on msm platforms should have IO_PAD_PWR_SWITCH bit set/unset
based on actual voltage used for IO lines. So when power irq is
triggered for io high or io low, the driver should check the voltages
supported and set the pad accordingly.
Signed-off-by: NKrishna Konda <kkonda@codeaurora.org>
Signed-off-by: NVenkat Gopalakrishnan <venkatg@codeaurora.org>
Signed-off-by: NVijay Viswanath <vviswana@codeaurora.org>
Reviewed-by: NDouglas Anderson <dianders@chromium.org>
Acked-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

During probe check whether the vdd-io regulator of sdhc platform device
can support 1.8V and 3V and store this information as a capability of
platform device.
Signed-off-by: NVijay Viswanath <vviswana@codeaurora.org>
Reviewed-by: NDouglas Anderson <dianders@chromium.org>
Acked-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Not all instances of the SDCC core supports changing signal voltage and
as such will not generate a power interrupt when the software attempts
to change the voltage. This results in probing the eMMC on some devices
to take over 2 minutes.

Check that the SWITCHABLE_SIGNALING_VOLTAGE bit in MCI_GENERICS is set
before waiting for the power interrupt.

Cc: Sahitya Tummala <stummala@codeaurora.org>
Cc: Vijay Viswanath <vviswana@codeaurora.org>
Fixes: c0309b38 ("mmc: sdhci-msm: Add sdhci msm register write APIs which wait for pwr irq")
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: NLuca Weiss <luca@z3ntu.xyz>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

The __WARN_printf() function is not portable across architectures
and causes a compile-time error on x86 and others that don't use
the asm-generic version of asm/bug.h:

drivers/mmc/host/sdhci-msm.c: In function 'sdhci_msm_check_power_status':
drivers/mmc/host/sdhci-msm.c:1066:4: error: implicit declaration of function '__WARN_printf'; did you mean '__dev_printk'? [-Werror=implicit-function-declaration]
    __WARN_printf("%s: pwr_irq for req: (%d) timed out\n",
    ^~~~~~~~~~~~~

The change that introduced this error, "mmc: sdhci-msm: Add sdhci msm
register write APIs which wait for pwr irq", likely meant to use
dev_warn(), so I'm changing over to that.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Register writes which change voltage of IO lines or turn the IO bus
on/off require controller to be ready before progressing further. When
the controller is ready, it will generate a power irq which needs to be
handled. The thread which initiated the register write should wait for
power irq to complete. This will be done through the new sdhc msm write
APIs which will check whether the particular write can trigger a power
irq and wait for it with a timeout if it is expected.
The SDHC core power control IRQ gets triggered when -
* There is a state change in power control bit (bit 0)
  of SDHCI_POWER_CONTROL register.
* There is a state change in 1.8V enable bit (bit 3) of
  SDHCI_HOST_CONTROL2 register.
* Bit 1 of SDHCI_SOFTWARE_RESET is set.

Also add support APIs which are used by sdhc msm write APIs to check
if power irq is expected to be generated and wait for the power irq
to come and complete if the irq is expected.

This patch requires CONFIG_MMC_SDHCI_IO_ACCESSORS to be enabled.
Signed-off-by: NSahitya Tummala <stummala@codeaurora.org>
Signed-off-by: NVijay Viswanath <vviswana@codeaurora.org>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

There is a rare scenario in HW, where the first clear pulse could
be lost when the actual reset and clear/read of status register
are happening at the same time. Fix this by retrying upto 10 times
to ensure the status register gets cleared. Otherwise, this will
lead to a spurious power IRQ which results in system instability.
Signed-off-by: NSahitya Tummala <stummala@codeaurora.org>
Signed-off-by: NVijay Viswanath <vviswana@codeaurora.org>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

SDCC controller reset (SW_RST) during probe may trigger power irq if
previous status of PWRCTL was either BUS_ON or IO_HIGH_V. So before we
enable the power irq interrupt in GIC (by registering the interrupt
handler), we need to ensure that any pending power irq interrupt status
is acknowledged otherwise power irq interrupt handler would be fired
prematurely.
Signed-off-by: NSubhash Jadavani <subhashj@codeaurora.org>
Signed-off-by: NVijay Viswanath <vviswana@codeaurora.org>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

The delay circuit used to support HS400 is calibrated based on two
additional clocks. When these clocks are not available and
FF_CLK_SW_RST_DIS is not set in CORE_HC_MODE, reset might fail. But on
some platforms this doesn't work properly and below dump can be seen in
the kernel log.

  mmc0: Reset 0x1 never completed.
  mmc0: sdhci: ============ SDHCI REGISTER DUMP ===========
  mmc0: sdhci: Sys addr:  0x00000000 | Version:  0x00001102
  mmc0: sdhci: Blk size:  0x00004000 | Blk cnt:  0x00000000
  mmc0: sdhci: Argument:  0x00000000 | Trn mode: 0x00000000
  mmc0: sdhci: Present:   0x01f80000 | Host ctl: 0x00000000
  mmc0: sdhci: Power:     0x00000000 | Blk gap:  0x00000000
  mmc0: sdhci: Wake-up:   0x00000000 | Clock:    0x00000002
  mmc0: sdhci: Timeout:   0x00000000 | Int stat: 0x00000000
  mmc0: sdhci: Int enab:  0x00000000 | Sig enab: 0x00000000
  mmc0: sdhci: AC12 err:  0x00000000 | Slot int: 0x00000000
  mmc0: sdhci: Caps:      0x742dc8b2 | Caps_1:   0x00008007
  mmc0: sdhci: Cmd:       0x00000000 | Max curr: 0x00000000
  mmc0: sdhci: Resp[0]:   0x00000000 | Resp[1]:  0x00000000
  mmc0: sdhci: Resp[2]:   0x00000000 | Resp[3]:  0x00000000
  mmc0: sdhci: Host ctl2: 0x00000000
  mmc0: sdhci: ============================================

Add support for the additional calibration clocks to allow these
platforms to be configured appropriately.

Cc: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Cc: Ritesh Harjani <riteshh@codeaurora.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: NRob Herring <robh@kernel.org>
Tested-by: NJeremy McNicoll <jeremymc@redhat.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

By stuffing the runtime controlled clocks into a clk_bulk_data array we
can utilize the newly introduced bulk clock operations and clean up the
error paths. This allow us to handle additional clocks in subsequent
patch, without the added complexity.

Cc: Ritesh Harjani <riteshh@codeaurora.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: NJeremy McNicoll <jeremymc@redhat.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Programming legacy HOST SDMA Buffer Boundary bits in Block Size Register
(0x04) is not supported in Qualcomm sdhci controllers. Writing to this
would cause the controller not to transfer last block in case block size
is 4 bytes or less.

This issue was noticed while testing sdio wlan card on Qcom DB410c board.
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Detected by sparse.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

The spin lock is not necessary in set_ios. Anything that is racing with
changes to the I/O state is already broken. The mmc core already provides
synchronization via "claiming" the host. So remove spin_lock and friends
from sdhci_set_ios and related callbacks.
Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
Tested-by: NLudovic Desroches <ludovic.desroches@microchip.com>

This removes CDC init sequence comments which are
not useful anyway.
Signed-off-by: NRitesh Harjani <riteshh@codeaurora.org>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

platform_execute_tuning should not really exist as it does not
do anything useful.

So remove this ops and directly plug sdhci_msm_execute_tuning
with mmc_host_ops.

Also in case of HS400 tuning clear SDHCI_HS400_TUNING flag once
HS400 related mode selection is done.
Signed-off-by: NRitesh Harjani <riteshh@codeaurora.org>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

This provides enhanced_strobe mode feature support in sdhci-msm
driver.
Signed-off-by: NRitesh Harjani <riteshh@codeaurora.org>
Tested-by: NJeremy McNicoll <jeremymc@redhat.com>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

During tuning execution for HS400 mode, HW sequence recommends
to select MCLK_SEL/2(0x3) in VENDOR_SPEC & sdhc msm clock at GCC
to be 400MHZ (nearest supported clk). Add this change in tuning
sequence during HS400 tuning.
Signed-off-by: NRitesh Harjani <riteshh@codeaurora.org>
Tested-by: NJeremy McNicoll <jeremymc@redhat.com>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Program CORE_CSR_CDC_DELAY_CFG for hardware recommended 1.25ns delay.
We may see data CRC errors if it's programmed for any other delay
value.
Signed-off-by: NSubhash Jadavani <subhashj@codeaurora.org>
Signed-off-by: NRitesh Harjani <riteshh@codeaurora.org>
Tested-by: NJeremy McNicoll <jeremymc@redhat.com>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

The vendor specific func register doesn't get reset when using the
software reset register. The various bootloader's could leave this
in an unknown state, hence reset this register to it's power on reset
value during probe.
Signed-off-by: NVenkat Gopalakrishnan <venkatg@codeaurora.org>
Signed-off-by: NRitesh Harjani <riteshh@codeaurora.org>
Tested-by: NJeremy McNicoll <jeremymc@redhat.com>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Factor out sdhci_msm_hs400 used for DLL calibration in HS400
modes. This function will be needed for enhanced_strobe as well.
Signed-off-by: NRitesh Harjani <riteshh@codeaurora.org>
Tested-by: NJeremy McNicoll <jeremymc@redhat.com>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Factor out msm_set/get_clock_rate_for_bus_mode for it's later
use in changing the tuning sequence for selecting HS400
bus speed mode.
Signed-off-by: NRitesh Harjani <riteshh@codeaurora.org>
Tested-by: NJeremy McNicoll <jeremymc@redhat.com>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

This factors out sdhci_msm_hc_select_mode to later use
it during enhanced_strobe mode select.
It also further breaks sdhci_msm_hc_select_mode
into separate functions for configuring HS400 mode
or other modes.
Signed-off-by: NRitesh Harjani <riteshh@codeaurora.org>
Tested-by: NJeremy McNicoll <jeremymc@redhat.com>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

The newer msm sdhci's cores use a different DLL hardware for HS400.
Update the configuration and calibration of the newer DLL block.

The HS400 DLL block used previously is CDC LP 533 and requires
programming multiple registers and waiting for configuration to
complete and then enable it. It has about 18 register writes and
two register reads.

The newer HS400 DLL block is SDC4 DLL and requires two register
writes for configuration and one register read to confirm that it
is initialized. There is an additional register write to enable
the power save mode for SDC4 DLL block.
Signed-off-by: NRitesh Harjani <riteshh@codeaurora.org>
Signed-off-by: NKrishna Konda <kkonda@codeaurora.org>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

In HS400 mode a new RCLK is introduced on the interface for read data
transfers. The eMMC5.0 device transmits the read data to the host with
respect to rising and falling edges of RCLK. In order to ensure correct
operation of read data transfers in HS400 mode, the incoming RX data
needs to be sampled by delayed version of RCLK.

The CDCLP533 delay circuit shifts the RCLK by T/4. It needs to be
initialized, configured and enabled once during HS400 mode switch and
when operational voltage/clock is changed.
Signed-off-by: NVenkat Gopalakrishnan <venkatg@codeaurora.org>
Signed-off-by: NRitesh Harjani <riteshh@codeaurora.org>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Save the tuning phase once the tuning is performed.
This phase value will be used while calibrating DLL
for HS400 mode.
Signed-off-by: NRitesh Harjani <riteshh@codeaurora.org>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

The following msm platform specific changes are added to support HS400.
- Allow tuning for HS400 mode.
- Configure HS400 timing mode using the VENDOR_SPECIFIC_FUNC register.
Signed-off-by: NVenkat Gopalakrishnan <venkatg@codeaurora.org>
Signed-off-by: NRitesh Harjani <riteshh@codeaurora.org>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

SDHC MSM controller need 2x clock for MCLK at GCC.
Hence make required changes to have 2x clock for
DDR timing modes.
Signed-off-by: NRitesh Harjani <riteshh@codeaurora.org>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

sdhci-msm controller may have different clk-rates for each
bus speed mode. Thus implement set_clock callback for
sdhci-msm driver.
Signed-off-by: NSahitya Tummala <stummala@codeaurora.org>
Signed-off-by: NRitesh Harjani <riteshh@codeaurora.org>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

sdhc-msm controller needs this SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN
& SDHCI_QUIRK2_PRESET_VALUE_BROKEN to be set. Hence setting it.
Signed-off-by: NSahitya Tummala <stummala@codeaurora.org>
Signed-off-by: NRitesh Harjani <riteshh@codeaurora.org>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

This add get_min_clock() and get_max_clock() callback
for sdhci-msm. sdhci-msm min/max clocks may be different
hence implement these callbacks.
Signed-off-by: NSahitya Tummala <stummala@codeaurora.org>
Signed-off-by: NRitesh Harjani <riteshh@codeaurora.org>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

SDCC core with minor version >= 0x42 introduced new 14lpp
DLL. This has additional requirements in the reset sequence
for DLL tuning. Make necessary changes as needed.

Without this patch we see below errors on such SDHC controllers
	sdhci_msm 7464900.sdhci: mmc0: DLL failed to LOCK
	mmc0: tuning execution failed: -110
Signed-off-by: NVenkat Gopalakrishnan <venkatg@codeaurora.org>
Signed-off-by: NRitesh Harjani <riteshh@codeaurora.org>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

This patch changes the poor style of writel/readl registers
into more readable format. This avoid mixed style format
of readl/writel in sdhci-msm driver.
This patch also removes the one line comments which were present for
above writel/readl, since they were of no help.
Signed-off-by: NRitesh Harjani <riteshh@codeaurora.org>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Provides runtime PM callbacks to enable and disable clock resources
when idle. Also support system PM callbacks to be called during system
suspend and resume.
Reviewed-by: NRitesh Harjani <riteshh@codeaurora.org>
Reviewed-by: NGeorgi Djakov <georgi.djakov@linaro.org>
Tested-by: NRitesh Harjani <riteshh@codeaurora.org>
Signed-off-by: NPramod Gurav <pramod.gurav@linaro.org>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Fix to return a negative error code from the platform_get_irq_byname()
error handling case instead of 0, as done elsewhere in this function.

Fixes: ad81d387 ("mmc: sdhci-msm: Add support for UHS cards")
Signed-off-by: NWei Yongjun <weiyongjun1@huawei.com>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Acked-by: NGeorgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Enabling support for ultra high speed mode cards requires some
voltage switching and interaction with the PMIC via a special
power IRQ. Add support for this.
Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>