1. 08 11月, 2012 3 次提交
    • I
      PCI: Add workaround for PLX PCI 9050 BAR alignment erratum · 21c5fd97
      Ian Abbott 提交于
      The PLX PCI 9050 PCI Target bridge controller has a bug that prevents
      its local configuration registers being read through BAR0 (memory) or
      BAR1 (i/o) if the base address lies on an odd 128-byte boundary, i.e. if
      bit 7 of the base address is non-zero.  This bug is described in the PCI
      9050 errata list, version 1.4, May 2005.  It was fixed in the
      pin-compatible PCI 9052, which can be distinguished from the PCI 9050 by
      checking the revision in the PCI header, which is hard-coded for these
      chips.
      
      Workaround the problem by re-allocating the affected regions to a
      256-byte boundary.  Note that BAR0 and/or BAR1 may have been disabled
      (size 0) during initialization of the PCI chip when its configuration is
      read from a serial EEPROM.
      
      Currently, the fix-up has only been used for devices with the default
      vendor and device ID of the PLX PCI 9050.  The PCI 9052 shares the same
      default device ID as the PCI 9050 but they have different PCI revision
      codes.
      Signed-off-by: NIan Abbott <abbotti@mev.co.uk>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      21c5fd97
    • J
      PCI: Convert dev_printk(KERN_<LEVEL> to dev_<level>( · 438be3c6
      Joe Perches 提交于
      dev_<level> calls take less code than dev_printk(KERN_<LEVEL>
      and reducing object size is good.
      Coalesce formats for easier grep.
      Signed-off-by: NJoe Perches <joe@perches.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      438be3c6
    • D
      PCI: Don't touch card regs after runtime suspend D3 · 42eca230
      Dave Airlie 提交于
      If the driver takes care of state saving, don't touch any registers on it.
      
      Optimus (dual-gpu) laptops seem to have their own form of D3cold, but
      unfortunately enter it on normal D3 transitions via the ACPI callback.
      
      So when we use runtime PM to transition to D3, the card disappears off
      the PCI bus, however we then try to access registers on it in the
      runtime suspend finish, which really doesn't work.
      
      This patch checks whether the pci state is saved and doesn't attempt to hit
      any registers after that point if it is.
      
      (Looks okay to Rafael)
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      42eca230
  2. 26 10月, 2012 37 次提交
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