1. 21 5月, 2012 1 次提交
  2. 21 4月, 2012 3 次提交
  3. 17 4月, 2012 1 次提交
  4. 14 4月, 2012 1 次提交
  5. 31 3月, 2012 1 次提交
  6. 30 3月, 2012 1 次提交
    • L
      Fix ia64 build errors (fallout from system.h disintegration) · 93f37888
      Luck, Tony 提交于
      Fix this build error on ia64:
      
        In file included from include/linux/sched.h:92,
                        from arch/ia64/kernel/asm-offsets.c:9:
        include/linux/llist.h:59:25: error: asm/cmpxchg.h: No such file or directory
        make[1]: *** [arch/ia64/kernel/asm-offsets.s] Error 1
      
      Right now we don't seem to need any actual contents for the
      asm/cmpxchg.h to make the build work ...  so leave the migration of
      xchg() and cmpxchg() to this new header file for a future patch.
      
      Also process.c needs <asm/switch_to.h> (for definition of pfm_syst_info).
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      93f37888
  7. 29 3月, 2012 4 次提交
  8. 28 3月, 2012 1 次提交
  9. 27 3月, 2012 1 次提交
  10. 16 3月, 2012 1 次提交
  11. 15 3月, 2012 1 次提交
    • L
      [IA64] Fix ISA IRQ trigger model and polarity setting · 0577bb66
      Liu Jiang 提交于
      When handling Interrupt Source Override in MADT table, the default
      ISA IRQ trigger model and polarity should be edge-rising.
      Current IA64 implmentation doesn't follow the specification and
      set default ISA IRQ trigger model as level-low. With that wrong
      configuration and when system runs out of interrupt vectors,
      it will cause vector sharing among edge triggered ISA IRQ and
      level triggered PCI IRQ, then interrupt storm. So change the code
      to follow the specification.
      Signed-off-by: NLiu Jiang <jiang.liu@huawei.com>
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      0577bb66
  12. 11 3月, 2012 1 次提交
    • K
      xen/enlighten: Expose MWAIT and MWAIT_LEAF if hypervisor OKs it. · 73c154c6
      Konrad Rzeszutek Wilk 提交于
      For the hypervisor to take advantage of the MWAIT support it needs
      to extract from the ACPI _CST the register address. But the
      hypervisor does not have the support to parse DSDT so it relies on
      the initial domain (dom0) to parse the ACPI Power Management information
      and push it up to the hypervisor. The pushing of the data is done
      by the processor_harveset_xen module which parses the information that
      the ACPI parser has graciously exposed in 'struct acpi_processor'.
      
      For the ACPI parser to also expose the Cx states for MWAIT, we need
      to expose the MWAIT capability (leaf 1). Furthermore we also need to
      expose the MWAIT_LEAF capability (leaf 5) for cstate.c to properly
      function.
      
      The hypervisor could expose these flags when it traps the XEN_EMULATE_PREFIX
      operations, but it can't do it since it needs to be backwards compatible.
      Instead we choose to use the native CPUID to figure out if the MWAIT
      capability exists and use the XEN_SET_PDC query hypercall to figure out
      if the hypervisor wants us to expose the MWAIT_LEAF capability or not.
      
      Note: The XEN_SET_PDC query was implemented in c/s 23783:
      "ACPI: add _PDC input override mechanism".
      
      With this in place, instead of
       C3 ACPI IOPORT 415
      we get now
       C3:ACPI FFH INTEL MWAIT 0x20
      
      Note: The cpu_idle which would be calling the mwait variants for idling
      never gets set b/c we set the default pm_idle to be the hypercall variant.
      Acked-by: NJan Beulich <JBeulich@suse.com>
      [v2: Fix missing header file include and #ifdef]
      Signed-off-by: NKonrad Rzeszutek Wilk <konrad.wilk@oracle.com>
      73c154c6
  13. 09 3月, 2012 23 次提交