Fix an incorrect function name so the driver builds.
Signed-off-by: NMatthew Garrett <mjg@redhat.com>

When I added the buslock/unlock mechanism to the pmic code in order to
get rid of the horrible work queue stuff, stupid me missed to add the
new callbacks to the irq_chip.

In consequence Andrew removed the unused functions, but I missed that.

Add them back and hook them up proper.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Cc: Matthew Garrett <mjg@redhat.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: NMatthew Garrett <mjg@redhat.com>

Scripted with coccinelle.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

There is no need to install a chained handler for this hardware. This
is a plain x86 IOAPIC interrupt which is handled by the core code
perfectly fine. There is nothing special about demultiplexing these
gpio interrupts which justifies a custom hack. Replace it by a plain
old interrupt handler installed with request_irq. That makes the code
agnostic about the underlying primary interrupt hardware. The overhead
for this is minimal, but it gives us the advantage of accounting,
balancing and to detect interrupt storms. gpio interrupts are not
really that performance critical.

Patch fixups from akpm
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NMatthew Garrett <mjg@redhat.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>

The set_type function of the pmic irq chip is a horrible hack. It
schedules work because it cannot access the scu chip from the set_type
function. That breaks the assumption, that the type is set after
set_type has returned.

irq_chips provide buslock functions to avoid the above. Convert the
driver to use the proper model.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Cc: Feng Tang <feng.tang@intel.com>
Cc: Matthew Garrett <mjg@redhat.com>
Cc: Alan Cox <alan@linux.intel.com>
Cc: Alek Du <alek.du@intel.com>
Signed-off-by: NMatthew Garrett <mjg@redhat.com>

Old functions will go away soon. Remove the stray semicolons while at
it.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Cc: Feng Tang <feng.tang@intel.com>
Cc: Matthew Garrett <mjg@redhat.com>
Cc: Alan Cox <alan@linux.intel.com>
Cc: Alek Du <alek.du@intel.com>
Signed-off-by: NMatthew Garrett <mjg@redhat.com>

commit 456dc301([PATCH] intel_pmic_gpio: modify EOI handling following
change of kernel irq subsystem) changes

-	desc->chip->eoi(irq);
+
+	if (desc->chip->irq_eoi)
+		desc->chip->irq_eoi(irq_get_irq_data(irq));
+	else
+		dev_warn(pg->chip.dev, "missing EOI handler for irq %d\n", irq);

With the following explanation:

 "Latest kernel has many changes in IRQ subsystem and its interfaces,
  like adding irq_eoi" for struct irq_chip, this patch will make it
  support both the new and old interface."

This is completely bogus.

#1) The changelog does not match the patch at all

#2) This driver relies on the assumption that it sits behind an eoi
    capable interrupt line. If the implementation of the underlying
    chip changes from eoi to irq_eoi then this driver has to follow
    that change and not add a total bogosity.

Remove the sillyness and retrieve the interrupt data from irq_desc
directly. No need to got through circles to look it up.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Cc: Feng Tang <feng.tang@intel.com>
Cc: Matthew Garrett <mjg@redhat.com>
Cc: Alan Cox <alan@linux.intel.com>
Cc: Alek Du <alek.du@intel.com>
Signed-off-by: NMatthew Garrett <mjg@redhat.com>

Latest kernel has many changes in IRQ subsystem and its interfaces, like adding
"irq_eoi" for struct irq_chip, this patch will make it support both the new
and old interface.

Cc: Alek Du <alek.du@intel.com>
Signed-off-by: NFeng Tang <feng.tang@intel.com>
Signed-off-by: NMatthew Garrett <mjg@redhat.com>

Signed-off-by: NZimny Lech <napohybelskurwysynom2010@gmail.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

In pmic_irq_type(), we use gpio as array index for trigger,
thus the valid value range for gpio should be 0 .. NUM_GPIO - 1.
Signed-off-by: NAxel Lin <axel.lin@gmail.com>
Signed-off-by: NMatthew Garrett <mjg@redhat.com>

The intel_scu_ipc_update_register 2nd paramter should the bits and 3rd
paramter should be the mask.

This typo was introduced during IPC function changing...
Reported-by: NRyan Zhou <ryan.zhou@intel.com>
Signed-off-by: NAlek Du <alek.du@intel.com>
Signed-off-by: NAlan Cox <alan@linux.intel.com>
Signed-off-by: NMatthew Garrett <mjg@redhat.com>

Moorestown has PMIC chip which contains GPIO blocks. The PMIC chip is
connected to Langwell by SPI interface. So this GPIO driver will be regarded
as SPI GPIO expander though the actual GPIO access is through IPC and SRAM.
The SPI master contoller will probe this device driver by parsing SPIB table.

Cleaned up for new IPC, GPE removed and some printk and other tidying by
Alan Cox. Fixes for points noted by Matthew Garrett
Signed-off-by: NAlek Du <alek.du@intel.com>
Signed-off-by: NAlan Cox <alan@linux.intel.com>
Signed-off-by: NMatthew Garrett <mjg@redhat.com>