Simplify code by replacing custom code by generic helper and add missing
const qualifier to driver data structures.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NInki Dae <inki.dae@samsung.com>

Simplify code by replacing custom code by generic helper.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NInki Dae <inki.dae@samsung.com>

clock_enable callback is used only by FIMD->DP pipeline. Similar but more
universal functionality provides pipeline clock.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NInki Dae <daeinki@gmail.com>

According to documentation HDMI-PHY must be on prior to MIXER configuration.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NInki Dae <inki.dae@samsung.com>

According to documentation and tests HDMI-PHY must be on prior
to MIXER configuration.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>

Components belonging to the same pipeline often requires
synchronized clocks. Such clocks are sometimes provided
by external clock controller, but they can be also provided by
pipeline components. In latter case there should be a way
to access them from another component belonging to the same pipeline.
This is the case of:
- DECON,FIMD -> HDMI and HDMI-PHY clock,
- FIMD -> DP and DP clock in FIMD.
The latter case has been solved by clock_enable callback
in exynos_drm_crtc_ops. This solutin will not work with
HDMI path as in this case clock is provided by encoder.

This patch provides more generic solution allowing to register
pipeline clock during initialization in exynos_drm_crtc structure.
This way the clock will be easily accessible from both components.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NInki Dae <inki.dae@samsung.com>

The helper abstracts out conversion from pipeline
to crtc. Currently it is used in two places, but
there will be more uses in next patches.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NInki Dae <inki.dae@samsung.com>

decon_atomic_begin and decon_atomic_flush protects all windows already.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NInki Dae <inki.dae@samsung.com>

Resetting IP at starting ensures that DECON will be in known state
regardless of changes by bootloader.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NInki Dae <inki.dae@samsung.com>

DECON should be updated after un-protecting windows and after changing
output parameters, otherwise image is not displayed in case of HDMI path.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NInki Dae <inki.dae@samsung.com>

HDMI registry dump unnecessary spoils console and is not very helpful.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NInki Dae <inki.dae@samsung.com>

To ensure HDMI-PHY reprogramming will not affect
HDMI the latter should be reset.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NInki Dae <inki.dae@samsung.com>

HDMI-PHY power off bit defaults to 0 in older HDMI versions.
In case of Exynos5433 it defaults to 1. To make code
consistent across all versions this bit is always unset/set in
power on/off sequences.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NInki Dae <inki.dae@samsung.com>

Proper PHY configuration should be as follow:
1. set HDMI clock parents to OSCCLK.
2. reconfigure PHY.
3. set HDMI clock parents to PHY.
4. wait for PLL stabilization.

The patch fixes it and consolidates the code.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NInki Dae <inki.dae@samsung.com>

DECON-TV(Display and Enhancement Controller for TV) is a variation
of DECON IP. Its main purpose is to produce video stream for HDMI IP.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NInki Dae <inki.dae@samsung.com>

DECON IP requires this clock to access configuration registers.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NInki Dae <inki.dae@samsung.com>

HDMI on Exynos5433 differs from previous versions:
- different HDMI-PHY settings,
- different clocks,
- SYSREG registers for enabling reference clock,
- MODE_SET register in HDMI-PHY.
It is distinguished from other variants by different compatible string.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NInki Dae <inki.dae@samsung.com>

Exynos5433 variant of HDMI requires different set of clocks and sysreg
phandle to system registers.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NInki Dae <inki.dae@samsung.com>

There is no point in rewriting default values, as the IP is reset anyway.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NInki Dae <inki.dae@samsung.com>

The patch performs following clean-ups:
- remove unnecessary white spaces,
- remove obvious comments,
- fix tabulations,
- remove NULL initializators,
- re-order driver data.

The patch does not change driver's behavior.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NInki Dae <inki.dae@samsung.com>

HDMI-PHY configurations are stored as array pointer and count pair,
we can re-use existing helpers to simplify their initialization.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NInki Dae <inki.dae@samsung.com>

These variables should not be modified.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NInki Dae <inki.dae@samsung.com>

With incoming support for newer SoCs different set of clocks will be required,
depending on IP version. The patch prepares the driver for it.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NInki Dae <inki.dae@samsung.com>

Commit 254d4d11 ("drm/exynos: Add dependency for G2D in Kconfig") made
the DRM_EXYNOS_G2D symbol to only be selectable if the s5p-g2d V4L2 driver
is not enabled, since both use the same HW IP block.

But added the dependency as depends on !VIDEO_SAMSUNG_S5P_G2D which isn't
correct since Kconfig expressions are not boolean but tristate. So it will
only evaluate to 'n' if VIDEO_SAMSUNG_S5P_G2D=y but it will evaluate to m
if VIDEO_SAMSUNG_S5P_G2D=m.

This means that both the V4L2 and DRM drivers can be enabled if the former
is enabled as a module, which is not what we want.
Signed-off-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: NInki Dae <inki.dae@samsung.com>

The "ret = regmap_write()" assignment was missing so this error message
is never printed.
Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: NInki Dae <inki.dae@samsung.com>

We accidentally return success instead of a negative error code here.
Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: NInki Dae <inki.dae@samsung.com>

Commit 1feafd3a ("drm/exynos: add
exynos5420 support for fimd") add support for Exynos 5420 SoC, but it
broke enabling display clock feature because of incorrect condition
check. This patch fixes it, so display is working again on platforms
requiring display clock control (i.e. Exynos5250-based SNOW platform).
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NInki Dae <inki.dae@samsung.com>

Fbdev code should be compiled only if CONFIG_DRM_FBDEV_EMULATION option
is enabled. The patch fixes exynos-drm code trying to manipulate
fbdev data which is not initialized in case CONFIG_DRM_FBDEV_EMULATION
is disabled.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NInki Dae <inki.dae@samsung.com>

exynos_plane_mode_set should use adjusted_mode from the same atomic state as
plane state. Otherwise it will result in incorrect behavior in case
crtc mode changes.

The patch fixes bug with black console framebuffer in case of command mode
panels.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NInki Dae <inki.dae@samsung.com>

gcc-6 warns about a pointless loop in exynos_drm_subdrv_open:

drivers/gpu/drm/exynos/exynos_drm_core.c: In function 'exynos_drm_subdrv_open':
drivers/gpu/drm/exynos/exynos_drm_core.c:104:199: error: self-comparison always evaluates to false [-Werror=tautological-compare]
  list_for_each_entry_reverse(subdrv, &subdrv->list, list) {

Here, the list_for_each_entry_reverse immediately terminates because
the subdrv pointer is compared to itself as the loop end condition.

If we were to take the current subdrv pointer as the start of the
list (as we would do if list_for_each_entry_reverse() was not a macro),
we would iterate backwards over the &exynos_drm_subdrv_list anchor,
which would be even worse.

Instead, we need to use list_for_each_entry_continue_reverse()
to go back over each subdrv that was successfully opened until
the first entry.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NInki Dae <inki.dae@samsung.com>

This adds very rudimentary TCON (timing controller for raw LCD displays)
support to enable the bypass mode in order to use the DCU controller on
Freescale/NXP Vybrid SoC's.

Additionally the register clock and pixel clock has been separated, but
are currently still enabled and disabled pairwise.

Other than that, fixes and cleanups accross the driver.

* 'for-next' of http://git.agner.ch/git/linux-drm-fsl-dcu:
  drm/fsl-dcu: increment version and date
  drm/fsl-dcu: implement lastclose callback
  drm/fsl-dcu: disable output polling on driver unload
  drm/fsl-dcu: deallocate fbdev CMA on unload
  drm/fsl-dcu: use variable name dev for struct drm_device
  drm/fsl-dcu: handle missing panel gracefully
  drm/fsl-dcu: detach panel on destroy
  drm/layerscape: reduce excessive stack usage
  drm/fsl-dcu: add TCON driver
  drm/fsl-dcu: use common clock framework for pixel clock divider
  drm/fsl-dcu: add extra clock for pixel clock
  drm/fsl-dcu: disable clock on initialization failure and remove

Merge tag 'sun4i-drm-for-4.7' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into drm-next

Allwinner DRM driver for 4.7

This pull request introduces the sun4i driver, meant to be used on the
older Allwinner SoCs (A10, A13, A20, A23, A31 and A33).

It currently supports only the A13, which has one of the simplest video
pipeline. Support for other video components and SoCs will be added
eventually.

It supports only a RGB or composite output. It doesn't do HDMI, VGA, LVDS
or power management yet, but that will come in time as well.

* tag 'sun4i-drm-for-4.7' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
  MAINTAINERS: Add a maintainer for the Allwinner DRM driver
  drm: sun4i: tv: Add NTSC output standard
  drm: sun4i: tv: Add PAL output standard
  drm: sun4i: Add composite output
  drm: sun4i: Add RGB output
  drm: Add Allwinner A10 Display Engine support
  drm: sun4i: Add DT bindings documentation
  drm: fb: Add seq_file definition

Add myself as the maintainer of the new Allwinner DRM driver.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Add the settings to support the NTSC standard.
Reviewed-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Now that we have support for the composite output, we can start adding new
supported standards. Start with PAL, and we will add other eventually.
Reviewed-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Some Allwinner SoCs have an IP called the TV encoder that is used to output
composite and VGA signals. In such a case, we need to use the second TCON
channel.

Add support for that TV encoder.
Reviewed-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

One of the A10 display pipeline possible output is an RGB interface to
drive LCD panels directly. This is done through the first channel of the
TCON that will output our video signals directly.
Reviewed-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The Allwinner A10 and subsequent SoCs share the same display pipeline, with
variations in the number of controllers (1 or 2), or the presence or not of
some output (HDMI, TV, VGA) or not.

Add a driver with a limited set of features for now, and we will hopefully
support all of them eventually
Reviewed-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The display pipeline of the Allwinner A10 is involving several loosely
coupled components.

Add a documentation for the bindings.
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Otherwise, building with DEBUG_FS enabled will trigger a build warning
because we're using a structure that has not been declared.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>