1. 27 8月, 2015 2 次提交
    • M
      irqchip/GIC: Convert to EOImode == 1 · 0b996fd3
      Marc Zyngier 提交于
      So far, GICv2 has been used with EOImode == 0. The effect of this
      mode is to perform the priority drop and the deactivation of the
      interrupt at the same time.
      
      While this works perfectly for Linux (we only have a single priority),
      it causes issues when an interrupt is forwarded to a guest, and when
      we want the guest to perform the EOI itself.
      
      For this case, the GIC architecture provides EOImode == 1, where:
      - A write to the EOI register drops the priority of the interrupt
        and leaves it active. Other interrupts at the same priority level
        can now be taken, but the active interrupt cannot be taken again
      - A write to the DIR marks the interrupt as inactive, meaning it can
        now be taken again.
      
      We only enable this feature when booted in HYP mode and that
      the device-tree reported a suitable CPU interface. Observable behaviour
      should remain unchanged.
      Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
      Reviewed-and-tested-by: NEric Auger <eric.auger@linaro.org>
      Cc: Christoffer Dall <christoffer.dall@linaro.org>
      Cc: Jiang Liu <jiang.liu@linux.intel.com>
      Cc: <linux-arm-kernel@lists.infradead.org>
      Cc: kvmarm@lists.cs.columbia.edu
      Cc: Jason Cooper <jason@lakedaemon.net>
      Link: http://lkml.kernel.org/r/1440604845-28229-4-git-send-email-marc.zyngier@arm.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>
      0b996fd3
    • M
      irqchip/GICv3: Convert to EOImode == 1 · 0b6a3da9
      Marc Zyngier 提交于
      So far, GICv3 has been used in with EOImode == 0. The effect of this
      mode is to perform the priority drop and the deactivation of the
      interrupt at the same time.
      
      While this works perfectly for Linux (we only have a single priority),
      it causes issues when an interrupt is forwarded to a guest, and when
      we want the guest to perform the EOI itself.
      
      For this case, the GIC architecture provides EOImode == 1, where:
      - A write to ICC_EOIR1_EL1 drops the priority of the interrupt and
        leaves it active. Other interrupts at the same priority level can
        now be taken, but the active interrupt cannot be taken again
      - A write to ICC_DIR_EL1 marks the interrupt as inactive, meaning
        it can now be taken again.
      
      This patch converts the driver to be able to use this new mode,
      depending on whether or not the kernel can behave as a hypervisor.
      No feature change.
      Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
      Reviewed-and-tested-by: NEric Auger <eric.auger@linaro.org>
      Cc: Christoffer Dall <christoffer.dall@linaro.org>
      Cc: Jiang Liu <jiang.liu@linux.intel.com>
      Cc: <linux-arm-kernel@lists.infradead.org>
      Cc: kvmarm@lists.cs.columbia.edu
      Cc: Jason Cooper <jason@lakedaemon.net>
      Link: http://lkml.kernel.org/r/1440604845-28229-2-git-send-email-marc.zyngier@arm.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>
      0b6a3da9
  2. 26 8月, 2015 2 次提交
  3. 12 8月, 2015 1 次提交
  4. 04 8月, 2015 1 次提交
    • J
      irqchip/gic: Ensure gic_cpu_if_up/down() programs correct GIC instance · 4c2880b3
      Jon Hunter 提交于
      Commit 32289506 ("irqchip: gic: Preserve gic V2 bypass bits in cpu
      ctrl register") added a new function, gic_cpu_if_up(), to program the
      GIC CPU_CTRL register. This function assumes that there is only one GIC
      instance present and hence always uses the chip data for the primary GIC
      controller. Although it is not common for there to be a secondary, some
      devices do support a secondary. Therefore, fix this by passing
      gic_cpu_if_up() a pointer to the appropriate chip data structure.
      
      Similarly, the function gic_cpu_if_down() only assumes that there is a
      single GIC instance present. Update this function so that an instance
      number is passed for the appropriate GIC and return an error code on
      failure. The vexpress TC2 (which has a single GIC) is currently the only
      user of this function and so update it accordingly. Note that because the
      TC2 only has a single GIC, the call to gic_cpu_if_down() should always
      be successful.
      Signed-off-by: NJon Hunter <jonathanh@nvidia.com>
      Reviewed-by: NMarc Zyngier <marc.zyngier@arm.com>
      Cc: <linux-arm-kernel@lists.infradead.org>
      Cc: Russell King <linux@arm.linux.org.uk>
      Cc: Nicolas Pitre <nicolas.pitre@linaro.org>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Link: http://lkml.kernel.org/r/1438332252-25248-2-git-send-email-jonathanh@nvidia.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>
      4c2880b3
  5. 30 7月, 2015 2 次提交
  6. 27 7月, 2015 1 次提交
  7. 22 6月, 2015 1 次提交
  8. 28 5月, 2015 1 次提交
  9. 25 4月, 2015 1 次提交
  10. 31 3月, 2015 3 次提交
  11. 30 3月, 2015 3 次提交
  12. 26 3月, 2015 1 次提交
  13. 15 3月, 2015 3 次提交
  14. 08 3月, 2015 2 次提交
  15. 05 2月, 2015 1 次提交
    • J
      MIPS: cevt-r4k: Drop GIC special case · ae58d882
      James Hogan 提交于
      The cevt-r4k driver used to call into the GIC driver to find whether the
      timer was pending, but only with External Interrupt Controller (EIC)
      mode, where the Cause.IP bits can't be used as they encode the interrupt
      priority level (Cause.RIPL) instead.
      
      However commit e9de688d ("irqchip: mips-gic: Support local
      interrupts") changed the condition from cpu_has_veic to gic_present.
      This fails on cores such as P5600 which have a GIC but the local
      interrupts aren't routable by the GIC, causing c0_compare_int_usable()
      to consider the interrupt unusable so r4k_clockevent_init() fails.
      
      The previous behaviour, added in commit 98b67c37 ("MIPS: Add EIC
      support for GIC."), wasn't really correct either as far as I can tell,
      since P5600 apparently supports EIC mode too, and in any case the use of
      Cause.TI with r2 should have been sufficient anyway since commit
      010c108d ("MIPS: PowerTV: Fix support for timer interrupts with > 64
      external IRQs").
      
      Therefore drop the call into the gic driver altogether, and add a
      comment in c0_compare_int_pending() to clarify that Cause.TI does get
      checked since MIPS r2.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Fixes: e9de688d ("irqchip: mips-gic: Support local interrupts")
      Reviewed-by: NAndrew Bresticker <abrestic@chromium.org>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Steven J. Hill <steven.hill@imgtec.com>
      Cc: Qais Yousef <qais.yousef@imgtec.com>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/9077/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      ae58d882
  16. 26 1月, 2015 2 次提交
  17. 21 1月, 2015 2 次提交
  18. 29 11月, 2014 1 次提交
  19. 26 11月, 2014 5 次提交
  20. 24 11月, 2014 3 次提交
  21. 17 9月, 2014 1 次提交
    • F
      irqchip: add irq-omap-intc.h header · eaacabc0
      Felipe Balbi 提交于
      OMAP INTC irqchip driver will be moved under
      drivers/irqchip/ soon but we still have a dependency
      with mach-omap2 when it comes to idle functions.
      
      In order to make it easy to share those function
      prototypes with OMAP PM code, we introduce this new
      header.
      
      To avoid modifying several board-files and some of
      the PM-related code, we just include the new header
      from common.h which was already included by all
      users of IRQ-related PM code.
      Signed-off-by: NFelipe Balbi <balbi@ti.com>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      eaacabc0
  22. 19 8月, 2014 1 次提交
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