- 28 8月, 2013 1 次提交
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由 Emilio López 提交于
With the recent move towards CLK_OF_DECLARE(...), the driver stopped initializing osc32k, which is compatible "fixed-clock". This is because we never called of_clk_init(NULL). Fix this by moving the only other simple clock (osc24M) to use CLK_OF_DECLARE(...) and call of_clk_init(NULL) to initialize both of them. Signed-off-by: NEmilio López <emilio@elopez.com.ar> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 24 8月, 2013 1 次提交
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由 Jisheng Zhang 提交于
Add missing iounmap to setup error path. Signed-off-by: NJisheng Zhang <jszhang@marvell.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 22 8月, 2013 1 次提交
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由 Mike Turquette 提交于
At some point changes to clk_set_rate and clk_set_parent introduced a bug whereby NULL struct clk pointers were treated as an error. This is in violation of the API in include/linux/clk.h. Reintroduce graceful handling of NULL clk's by bailing from clk_set_rate and clk_set_parent with return codes of zero. Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 21 8月, 2013 1 次提交
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git://git.xilinx.com/linux-xlnx由 Mike Turquette 提交于
arm: Xilinx Zynq clock changes for v3.12 Just small two changes where the first fixes documentation and the second improves code readability.
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- 20 8月, 2013 7 次提交
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由 Soren Brinkmann 提交于
Use more descriptive #defines for the minimum and maximum PLL feedback divider. Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Soren Brinkmann 提交于
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 James Hogan 提交于
Implement clk-mux remuxing if the CLK_SET_RATE_NO_REPARENT flag isn't set. This implements determine_rate for clk-mux to propagate to each parent and to choose the best one (like clk-divider this chooses the parent which provides the fastest rate <= the requested rate). The determine_rate op is implemented as a core helper function so that it can be easily used by more complex clocks which incorporate muxes. Signed-off-by: NJames Hogan <james.hogan@imgtec.com> Reviewed-by: NStephen Boyd <sboyd@codeaurora.org> Cc: Mike Turquette <mturquette@linaro.org> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 James Hogan 提交于
Add a CLK_SET_RATE_NO_REPARENT clock flag, which will prevent muxes being reparented during clk_set_rate. To avoid breaking existing platforms, all callers of clk_register_mux() are adjusted to pass the new flag. Platform maintainers are encouraged to remove the flag if they wish to allow mux reparenting on set_rate. Signed-off-by: NJames Hogan <james.hogan@imgtec.com> Reviewed-by: NStephen Boyd <sboyd@codeaurora.org> Cc: Mike Turquette <mturquette@linaro.org> Cc: Russell King <linux@arm.linux.org.uk> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Viresh Kumar <viresh.linux@gmail.com> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Haojian Zhuang <haojian.zhuang@linaro.org> Cc: Chao Xie <xiechao.mail@gmail.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: "Emilio López" <emilio@elopez.com.ar> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Andrew Chew <achew@nvidia.com> Cc: Doug Anderson <dianders@chromium.org> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Paul Walmsley <pwalmsley@nvidia.com> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Thomas Abraham <thomas.abraham@linaro.org> Cc: Tomasz Figa <t.figa@samsung.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Cc: spear-devel@list.st.com Cc: linux-tegra@vger.kernel.org Tested-by: NHaojian Zhuang <haojian.zhuang@gmail.com> Acked-by: Stephen Warren <swarren@nvidia.com> [tegra] Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> [sunxi] Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> [Zynq] Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 James Hogan 提交于
Add core support to allow clock implementations to select the best parent clock when rounding a rate, e.g. the one which can provide the closest clock rate to that requested. This is by way of adding a new clock op, determine_rate(), which is like round_rate() but has an extra parameter to allow the clock implementation to optionally select a different parent clock. The core then takes care of reparenting the clock when setting the rate. The parent change takes place with the help of some new private data members. struct clk::new_parent specifies a clock's new parent (NULL indicates no change), and struct clk::new_child specifies a clock's new child (whose new_parent member points back to it). The purpose of these are to allow correct walking of the future tree for notifications prior to actually reparenting any clocks, specifically to skip child clocks who are being reparented to another clock (they will be notified via the new parent), and to include any new child clock. These pointers are set by clk_calc_subtree(), and the new_child pointer gets cleared when a child is actually reparented to avoid duplicate POST_RATE_CHANGE notifications. Each place where round_rate() is called, determine_rate() is checked first and called in preference. This restructures a few of the call sites to simplify the logic into if/else blocks. Signed-off-by: NJames Hogan <james.hogan@imgtec.com> Reviewed-by: NStephen Boyd <sboyd@codeaurora.org> Cc: Mike Turquette <mturquette@linaro.org> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 James Hogan 提交于
Move some parent related functions up in clk.c so they can be used by the modifications in the following patch which enables clock reparenting during set_rate. No other changes are made so this patch makes no functional difference in isolation. This is separate from the following patch primarily to ease readability of that patch. Signed-off-by: NJames Hogan <james.hogan@imgtec.com> Reviewed-by: NStephen Boyd <sboyd@codeaurora.org> Cc: Mike Turquette <mturquette@linaro.org> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 James Hogan 提交于
Abstract access to the clock parent cache by defining clk_get_parent_by_index(clk, index). This allows access to parent clocks from clock drivers. Signed-off-by: NJames Hogan <james.hogan@imgtec.com> Reviewed-by: NStephen Boyd <sboyd@codeaurora.org> Cc: Mike Turquette <mturquette@linaro.org> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 17 8月, 2013 3 次提交
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由 Mike Turquette 提交于
These registration calls may be used by loadable modules. Export them. Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Fabio Estevam 提交于
clk_register_divider() needs to be exported so that it could be used in a module driver, otherwise we get the following error: ERROR: "clk_register_divider" [sound/soc/mxs/snd-soc-mxs.ko] undefined! Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Signed-off-by: NMike Turquette <mturquette@linaro.org> [mturquette@linaro.org: also export clk_register_divider_table]
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由 Stephen Boyd 提交于
Export this symbol so that modules can register fixed rate clocks. Signed-off-by: NStephen Boyd <sboyd@codeaurora.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 09 8月, 2013 16 次提交
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由 Sachin Kamat 提交于
__initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Sachin Kamat 提交于
__initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Acked-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Sachin Kamat 提交于
__initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Acked-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Sachin Kamat 提交于
__initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Tested-by: NStephen Warren <swarren@nvidia.com> Acked-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Sachin Kamat 提交于
__initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Sachin Kamat 提交于
__initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Sachin Kamat 提交于
__initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Sachin Kamat 提交于
__initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Yadwinder Singh Brar 提交于
This patch adds support to register three(AP/CP/BT) buffered 32.768 KHz outputs of mfd-s2mps11 with common clock framework. Signed-off-by: NYadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Sachin Kamat 提交于
'exynos5420_plls' is used only in this file. Make is static. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Sachin Kamat 提交于
exynos5250_plls is used only in this file. Make it static. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Sachin Kamat 提交于
'exynos4_plls' is used only in this file. Make it static. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Fabio Estevam 提交于
Fix the following sparse warning: drivers/clk/mxs/clk-imx23.c:102:12: warning: symbol 'mx23_clocks_init' was not declared. Should it be static? Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Acked-by: NShawn Guo <shawn.guo@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Axel Lin 提交于
clk_register_composite() and clk_register_factors() return ERR_PTR on error. Signed-off-by: NAxel Lin <axel.lin@ingics.com> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Mike Turquette 提交于
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由 Sachin Kamat 提交于
Fixes a trivial typo. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 06 8月, 2013 3 次提交
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由 Tomasz Figa 提交于
This patch adds new, Common Clock Framework-based clock driver for Samsung S3C64xx SoCs. The driver is just added, without actually letting the platforms use it yet, since this requires more intermediate steps. Signed-off-by: NTomasz Figa <tomasz.figa@gmail.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Tomasz Figa 提交于
This patch adds support for PLL6552 and PLL6553 PLLs present on Samsung S3C64xx SoCs. Signed-off-by: NTomasz Figa <tomasz.figa@gmail.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Tomasz Figa 提交于
Some platforms have read-only clock muxes that are preconfigured at reset and cannot be changed at runtime. This patch extends mux clock driver to allow handling such read-only muxes by adding new CLK_MUX_READ_ONLY mux flag. Signed-off-by: NTomasz Figa <tomasz.figa@gmail.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 03 8月, 2013 7 次提交
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由 Vikas Sajjan 提交于
Adds the EPLL and VPLL freq table for exynos5250 SoC. Signed-off-by: NVikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: NYadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Vikas Sajjan 提交于
While trying to get rate of "mout_vpllsrc" MUX (parent) for registering the "fout_vpll" (child), we found get rate was failing. So this patch moves the mout_vpllsrc MUX out of the existing common list and registers the mout_vpllsrc MUX before the PLL registrations. Reviewed-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NVikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: NYadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Vikas Sajjan 提交于
This patch adds set_rate and round_rate clk_ops for PLL36xx Reviewed-by: NTomasz Figa <t.figa@samsung.com> Reviewed-by: NDoug Anderson <dianders@chromium.org> Signed-off-by: NVikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Yadwinder Singh Brar 提交于
This patch add set_rate() and round_rate() for PLL35xx Reviewed-by: NDoug Anderson <dianders@chromium.org> Reviewed-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NYadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Yadwinder Singh Brar 提交于
This patch defines a common rate_table which will contain recommended p, m, s, k values for supported rates that needs to be changed for changing corresponding PLL's rate. Reviewed-by: NDoug Anderson <dianders@chromium.org> Signed-off-by: NYadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Yadwinder Singh Brar 提交于
This patch removes samsung_clk_register_pll35xx() and samsung_clk_register_pll36xx() registaration functions as users migrated to new samsung_clk_register_pll(). Signed-off-by: NYadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Yadwinder Singh Brar 提交于
This patch migrates exynos5420 pll registeration to use common samsung_clk_register_pll() by intialising table of PLLs and adding PLLs to unique id list of clocks. Signed-off-by: NYadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: NVikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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