Do some initial cleanup, more probably will come.

- Move credits section to the end
- Update maintainers
- Drop sourceforge reference - project is long upstream now
- Reformat sections
- Reformat paragraphs
- Clarify text
- Bring it up-to-date
- Drop useless "future hardware scanning" section
Signed-off-by: NBorislav Petkov <bp@suse.de>

Fix various typos in Documentation/edac.txt.
Signed-off-by: NRami Rosen <ramirose@gmail.com>
Link: http://lkml.kernel.org/r/1434694714-2924-1-git-send-email-ramirose@gmail.comSigned-off-by: NBorislav Petkov <bp@suse.de>

Add support for the Arria10 SDRAM EDAC. Update the bindings document for
the new match string.
Signed-off-by: NThor Thayer <tthayer@opensource.altera.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: devicetree@vger.kernel.org
Cc: dinguyen@opensource.altera.com
Cc: galak@codeaurora.org
Cc: grant.likely@linaro.org
Cc: ijc+devicetree@hellion.org.uk
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: m.chehab@samsung.com
Cc: mark.rutland@arm.com
Cc: pawel.moll@arm.com
Cc: robh+dt@kernel.org
Cc: tthayer.linux@gmail.com
Link: http://lkml.kernel.org/r/1433428128-7292-5-git-send-email-tthayer@opensource.altera.comSigned-off-by: NBorislav Petkov <bp@suse.de>

Simple LAN device for debug or management purposes.
Device supports interrupts for RX and TX(completion).
Device does not have DMA ability.
Signed-off-by: NNoam Camus <noamc@ezchip.com>
Signed-off-by: NTal Zilcer <talz@ezchip.com>
Acked-by: NAlexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Add constants and callback functions for the dwmac on rk3368 socs.
As can be seen, the base structure is the same, only registers and
the bits in them moved slightly.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Signed-off-by: NWei Fang <fangwei1@huawei.com>
Signed-off-by: NJonathan Corbet <corbet@lwn.net>

Add sama5d2 to the biding documentation for this use of the GEM IP.
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

On sama5d4, we only have a GEM IP that is configured to do 10/100 Mbits. So the
use of "Gigabit" can be confusing.
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

In the driver and the DT bindings we use the "atmel" prefix. Fix it in the
binding documentation.
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

The following was seen in linux-next build coverage, which is somewhat
unique since it uses powerpc host to cross compile x86:

Documentation/mic/mpssd/mpssd.c:93:10: error: braced-group within expression allowed only inside a function
Documentation/mic/mpssd/mpssd.c:96:10: error: braced-group within expression allowed only inside a function
Documentation/mic/mpssd/mpssd.c:113:10: error: braced-group within expression allowed only inside a function
Documentation/mic/mpssd/mpssd.c:116:10: error: braced-group within expression allowed only inside a function
Documentation/mic/mpssd/mpssd.c:119:3: error: initializer element is not constant
Documentation/mic/mpssd/mpssd.c:119:3: error: (near initialization for 'virtnet_dev_page.host_features')
Documentation/mic/mpssd/mpssd.c:146:10: error: braced-group within expression allowed only inside a function
Documentation/mic/mpssd/mpssd.c:149:3: error: initializer element is not constant
Documentation/mic/mpssd/mpssd.c:149:3: error: (near initialization for 'virtblk_dev_page.host_features')
Documentation/mic/mpssd/mpssd.c:151:3: error: initializer element is not constant
Documentation/mic/mpssd/mpssd.c:151:3: error: (near initialization for 'virtblk_dev_page.blk_config.seg_max')
Documentation/mic/mpssd/mpssd.c:152:3: error: initializer element is not constant
Documentation/mic/mpssd/mpssd.c:152:3: error: (near initialization for 'virtblk_dev_page.blk_config.capacity')
make[5]: *** [Documentation/mic/mpssd/mpssd.o] Error 1

Since it is building /usr/sbin/mpssd and /usr/sbin/micctrl
for x86_64 and the original authors indicated[1] that:

   MIC card is expected to work with x86_64 host, not with ppc64.
   We have never compiled on ppc host..

so it probably makes sense to just skip building these userspace
programs when we are cross compiling.

[1] https://lists.ozlabs.org/pipermail/linuxppc-dev/2014-December/123296.html

Cc: Jonathan Corbet <corbet@lwn.net>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Cc: Sudeep Dutt <sudeep.dutt@intel.com>
Cc: Caz Yokoyama <Caz.Yokoyama@intel.com>
Cc: linux-doc@vger.kernel.org
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: NJonathan Corbet <corbet@lwn.net>

The following was seen in linux-next build coverage, which is somewhat
unique since it uses powerpc host to cross compile x86:

Documentation/prctl/disable-tsc-on-off-stress-test.c:36:1: error:
 impossible register constraint in 'asm'
Documentation/prctl/disable-tsc-ctxt-sw-stress-test.c:34:1: error:
 impossible register constraint in 'asm'
Documentation/prctl/disable-tsc-test.c:36:1: error: impossible
 register constraint in 'asm'

It probably makes sense to just skip building these tests when
we are cross compiling.

Cc: Jonathan Corbet <corbet@lwn.net>
Cc: linux-doc@vger.kernel.org
Cc: Erik Bosman <ejbosman@cs.vu.nl>
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: NJonathan Corbet <corbet@lwn.net>

The following was seen in linux-next build coverage, which is somewhat
unique since it uses powerpc host to cross compile x86:

Documentation/vDSO/vdso_standalone_test_x86.c:49:2: error: impossible
register constraint in 'asm'
make[4]: *** [Documentation/vDSO/vdso_standalone_test_x86.o] Error 1

It probably makes sense to just skip building these tests when
we are cross compiling.

Cc: Jonathan Corbet <corbet@lwn.net>
Cc: linux-doc@vger.kernel.org
Cc: Andy Lutomirski <luto@amacapital.net>
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: NJonathan Corbet <corbet@lwn.net>

This patch fix some spelling typo in sysfs-bus-fcoe
Signed-off-by: NMasanari Iida <standby24x7@gmail.com>
Signed-off-by: NJonathan Corbet <corbet@lwn.net>

Recently wikipedia announced to secure access to the servers.
Now all http access re-route to https.
Signed-off-by: NMasanari Iida <standby24x7@gmail.com>
Signed-off-by: NJonathan Corbet <corbet@lwn.net>

Recently wikipedia announced to secure access to the servers.
Now all http access re-route to https.
Signed-off-by: NMasanari Iida <standby24x7@gmail.com>
Signed-off-by: NJonathan Corbet <corbet@lwn.net>

The PCI based UART can be specified for earlyprintk with the 'pciserial'
parameter from the ea9e9d80. This patch adds missing information about
this parameter.
Signed-off-by: NAlexander Kuleshov <kuleshovmail@gmail.com>
Signed-off-by: NJonathan Corbet <corbet@lwn.net>

This patch fix a spelling typo in Documentation/pps/pps.txt
Signed-off-by: NMasanari Iida <standby24x7@gmail.com>
Acked-by: NRodolfo Giometti <giometti@enneenne.com>
[jc: did s/into/in the/ on the same line while we were there]
Signed-off-by: NJonathan Corbet <corbet@lwn.net>

The header install makefile creates an 'include' directory inside
INSTALL_HDR_PATH and appending include to the path results in headers
being installed to include/include.

Don't recommend appending include to the path as makefile already does
this.
Signed-off-by: NAnish Bhatt <anish@chelsio.com>
Signed-off-by: NJonathan Corbet <corbet@lwn.net>

On few platforms, for power efficiency, we want the device to be
configured for a specific OPP while we put the device in suspend state.

Add an optional property in operating-points-v2 bindings for that.
Suggested-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org>
Acked-by: NNishanth Menon <nm@ti.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>

On some platforms (Like Qualcomm's SoCs), it is not decided until
runtime on what OPPs to use. The OPP tables can be fixed at compile
time, but which table to use is found out only after reading some efuses
(sort of an prom) and knowing characteristics of the SoC.

To support such platform we need to pass multiple OPP tables per device
and hardware should be able to choose one and only one table out of
those.

Update operating-points-v2 bindings to support that.
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>

Current OPP (Operating performance point) device tree bindings have been
insufficient due to the inflexible nature of the original bindings. Over
time, we have realized that Operating Performance Point definitions and
usage is varied depending on the SoC and a "single size (just frequency,
voltage) fits all" model which the original bindings attempted and
failed.

The proposed next generation of the bindings addresses by providing a
expandable binding for OPPs and introduces the following common
shortcomings seen with the original bindings:

- Getting clock/voltage/current rails sharing information between CPUs.
  Shared by all cores vs independent clock per core vs shared clock per
  cluster.

- Support for specifying current levels along with voltages.

- Support for multiple regulators.

- Support for turbo modes.

- Other per OPP settings: transition latencies, disabled status, etc.?

- Expandability of OPPs in future.

This patch introduces new bindings "operating-points-v2" to get these problems
solved. Refer to the bindings for more details.

We now have multiple versions of OPP binding and only one of them should
be used per device.
Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: NRob Herring <robh@kernel.org>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Acked-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>

Add device tree bindings for the DA9063 OnKey driver.
Signed-off-by: NSteve Twiss <stwiss.opensource@diasemi.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Signed-off-by: NRichard Fitzgerald <rf@opensource.wolfsonmicro.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Fix typo in 'Multifunction'.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

This patch adds device tree binding documentation for
the flash cell of the Maxim max77693 multifunctional device.
Signed-off-by: NJacek Anaszewski <j.anaszewski@samsung.com>
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Acked-by: NSakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Add hwmon driver for the Microchip TC74.

The TC74 is a single-input 8-bit I2C temperature sensor,
with +-2 degrees centigrade accuracy.
Signed-off-by: NMaciej Szmigiero <mail@maciej.szmigiero.name>
Signed-off-by: NGuenter Roeck <linux@roeck-us.net>

Add DT bindings documentation for the new marvell-cesa driver.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

We are about to add a new driver to support new features like using the
TDMA engine to offload the CPU.
Orion, Dove and Kirkwood platforms are already using the mv_cesa driver,
but Orion SoCs do not embed the TDMA engine, which means we will have to
differentiate them if we want to get TDMA support on Dove and Kirkwood.
In the other hand, the migration from the old driver to the new one is not
something all people are willing to do without first auditing the new
driver.
Hence we have to support the new compatible in the mv_cesa driver so that
new platforms with updated DTs can still attach their crypto engine device
to this driver.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

The mv_cesa driver currently expects the SRAM memory region to be passed
as a platform device resource.

This approach implies two drawbacks:
- the DT representation is wrong
- the only one that can access the SRAM is the crypto engine

The last point is particularly annoying in some cases: for example on
armada 370, a small region of the crypto SRAM is used to implement the
cpuidle, which means you would not be able to enable both cpuidle and the
CESA driver.

To address that problem, we explicitly define the SRAM device in the DT
and then reference the sram node from the crypto engine node.

Also note that the old way of retrieving the SRAM memory region is still
supported, or in other words, backward compatibility is preserved.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

On Dove platforms, the crypto engine requires a clock. Document this
clocks property in the mv_cesa bindings doc.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

This patch changes the syscall handler to doom (tabort) active
transactions when a syscall is made and return very early without
performing the syscall and keeping side effects to a minimum (no CPU
accounting or system call tracing is performed). Also included is a
new HWCAP2 bit, PPC_FEATURE2_HTM_NOSC, to indicate this
behaviour to userspace.

Currently, the system call instruction automatically suspends an
active transaction which causes side effects to persist when an active
transaction fails.

This does change the kernel's behaviour, but in a way that was
documented as unsupported.  It doesn't reduce functionality as
syscalls will still be performed after tsuspend; it just requires that
the transaction be explicitly suspended.  It also provides a
consistent interface and makes the behaviour of user code
substantially the same across powerpc and platforms that do not
support suspended transactions (e.g. x86 and s390).

Performance measurements using
http://ozlabs.org/~anton/junkcode/null_syscall.c indicate the cost of
a normal (non-aborted) system call increases by about 0.25%.
Signed-off-by: NSam Bobroff <sam.bobroff@au1.ibm.com>
Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>

ACPI device ID arrays normally don't need to be written to as they're
only ever read. The common usage -- embedding pointers to acpi_device_id
arrays in other data structures -- reference them as 'const', e.g. as in
struct acpi_driver / acpi_scan_handler / device_driver. The matchers are
taking const pointers, too. So it's only natural, to propose using const
arrays. Change the documentation accordingly.
Signed-off-by: NMathias Krause <minipli@googlemail.com>
Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>

Document how the ACPI device enumeration code uses the special
PRP0001 device ID.
Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: NHanjun Guo <hanjun.guo@linaro.org>
Reviewed-by: NDarren Hart <dvhart@linux.intel.com>

Add sama5d2 support to irq-atmel-aic5.
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Cc: Boris BREZILLON <boris.brezillon@free-electrons.com>
Cc: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Cc: Ludovic Desroches <ludovic.desroches@atmel.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: <linux-arm-kernel@lists.infradead.org>
Link: http://lkml.kernel.org/r/1434632855-27272-1-git-send-email-nicolas.ferre@atmel.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

I copied the wrong shell code into the documentation. Sorry to all who
tried to get sense out of this current example :/ Slight rewording while
we are here.
Reported-by: NTim Bakker <bakkert@mymail.vcu.edu>
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
Cc: stable@kernel.org

The rk3368 is the first ARM64 soc from Rockchip, but seems to share most
peripherals with the ARM32 soc, including the pinctrl functionality.
The only notable difference is - as with every Rockchip soc - that the
offsets in the General Register Files moved around and a split of the pmu
section of the rk3288 into pmu and pmugrf (pmu general register files)
sections. The pinctrl driver of course only needs the pmugrf registers
for controlling the pin settings.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

- add new property "atmel,fifo-size"
- change "cs-gpios" to optional for SPI controller version >= 2.

Please be aware that the VERSION register can not be used to guess the
size of FIFOs. Indeed, for a given hardware version, the SPI controller
can be integrated on Atmel SoCs with different FIFO sizes. Also the
"atmel,fifo-size" property is optional as older SPI controllers don't
embed FIFO at all.

Besides, the FIFO size can not be read or guessed from other registers:
When designing the FIFO feature, no dedicated registers were added to
store this size. Unused spaces in the I/O register range are limited and
better reserved for future usages. Instead, the FIFO size of each
peripheral is documented in the programmer datasheet.

Finally, on a given SoC, there can be several instances of the SPI
controller with different FIFO sizes. This explain why we'd rather use a
dedicated DT property than use the "compatible" property.

For instance, sama5d2x SoCs come with some SPI controllers, the ones
inside Flexcoms, integrating 32 data FIFOs whereas other SPI controllers
use 16 data FIFOs. All these SPI controllers share the same IP version.
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Add an SPMI regulator driver for Qualcomm's PM8841, PM8941, and
PM8916 PMICs. This driver is based largely on code from
codeaurora.org[1].

[1] https://www.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/drivers/regulator/qpnp-regulator.c?h=msm-3.10
Cc: David Collins <collinsd@codeaurora.org>
Cc: <devicetree@vger.kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMark Brown <broonie@kernel.org>

Add PFC support for  the  R8A7794 SoC  including pin groups for some
on-chip devices such as ETH, I2C, INTC, MSIOF, QSPI, [H]SCIF...

Sergei: squashed together several patches, fixed the MLB_CLK typo,
added IRQ4.. IRQ9 pin groups, fixed IRQn comments, added ETH B pin
group names, removed stray new line and fixed typos in the  comments
in the pinmux_config_regs[] initializer, removed the platform device
ID, took into account limited number of signals in the GPIO1/5/6
controllers, added reasonable and removed unreasonable
copyrights, modified the bindings document, renamed, added changelog.

Changes in version 5:
- resolved rejects, refreshed the patch;
- added Laurent Pinchart's ACK.

Changes in version 4:
- reused the PORT_GP_26() macro to #define PORT_GP_28().

Changes in version 3:
- removed the platform device ID;
- added PORT_GP_26() and PORT_GP_28() macros, used them for GPIO1/5/6 in the
  CPU_ALL_PORT() macro.

Changes in version 2:
- rebased the patch.
Signed-off-by: NHisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>