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  1. 22 7月, 2020 2 次提交
    • R
      phy: armada-38x: fix NETA lockup when repeatedly switching speeds · 1dea06cd
      由 Russell King 提交于 
      The mvneta hardware appears to lock up in various random ways when
repeatedly switching speeds between 1G and 2.5G, which involves
reprogramming the COMPHY.  It is not entirely clear why this happens,
but best guess is that reprogramming the COMPHY glitches mvneta clocks
causing the hardware to fail.  It seems that rebooting resolves the
failure, but not down/up cycling the interface alone.

Various other approaches have been tried, such as trying to cleanly
power down the COMPHY and then take it back through the power up
initialisation, but this does not seem to help.

It was finally noticed that u-boot's last step when configuring a
COMPHY for "SGMII" mode was to poke at a register described as
"GBE_CONFIGURATION_REG", which is undocumented in any external
documentation.  All that we have is the fact that u-boot sets a bit
corresponding to the "SGMII" lane at the end of COMPHY initialisation.

Experimentation shows that if we clear this bit prior to changing the
speed, and then set it afterwards, mvneta does not suffer this problem
on the SolidRun Clearfog when switching speeds between 1G and 2.5G.

This problem was found while script-testing phylink.

This fix also requires the corresponding change to DT to be effective.
See "ARM: dts: armada-38x: fix NETA lockup when repeatedly switching
speeds".

Fixes: 14dc100b ("phy: armada38x: add common phy support")
Signed-off-by: NRussell King <rmk+kernel@armlinux.org.uk>
Reviewed-by: NAndrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/E1jxtRj-0003Tz-CG@rmk-PC.armlinux.org.ukSigned-off-by: NVinod Koul <vkoul@kernel.org>
      1dea06cd
    • R
      dt: update Marvell Armada 38x COMPHY binding · 6c89533d
      由 Russell King 提交于 
      Update the Marvell Armada 38x COMPHY binding with an additional
optional register pair describing the location of an undocumented
system register controlling something to do with the Gigabit Ethernet
and COMPHY.  There is one bit for each COMPHY lane that may be using
the serdes, but exactly what this register does is completely unknown.

This register only appears to exist on Armada 38x devices, and not
other SoCs using the NETA ethernet block, so it seems logical that it
should be part of the COMPHY.

This is also how u-boot groups this register; it is dealt with as part
of the COMPHY initialisation there.

However, at the end of the day, due to the undocumented nature of this
register, we can only guess.
Signed-off-by: NRussell King <rmk+kernel@armlinux.org.uk>
Acked-by: NRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/E1jxtRZ-0003Ta-4h@rmk-PC.armlinux.org.ukSigned-off-by: NVinod Koul <vkoul@kernel.org>
      6c89533d
  3. 21 7月, 2020 1 次提交
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  17. 25 6月, 2020 2 次提交