- 17 9月, 2020 2 次提交
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由 Shengjiu Wang 提交于
fsl_sai_check_version can help to parse the version info in VERID and PARAM registers. Signed-off-by: NShengjiu Wang <shengjiu.wang@nxp.com> Acked-by: NNicolin Chen <nicoleotsuka@gmail.com> Reviewed-by: NFabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/1600323079-5317-3-git-send-email-shengjiu.wang@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>
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由 Shengjiu Wang 提交于
On i.MX8MQ/i.MX8MN/i.MX8MM platform, the sai IP is upgraded. There are some new registers and new bit definition. This patch is to complete the register list. Signed-off-by: NShengjiu Wang <shengjiu.wang@nxp.com> Acked-by: NNicolin Chen <nicoleotsuka@gmail.com> Reviewed-by: NFabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/1600323079-5317-2-git-send-email-shengjiu.wang@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>
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- 03 9月, 2020 2 次提交
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由 Shengjiu Wang 提交于
Transmit data pins will output zero when slots are masked or channels are disabled. In CHMOD TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled. When data pins are tri-stated, there is noise on some channels when FS clock value is high and data is read while fsclk is transitioning from high to low. Signed-off-by: NCosmin-Gabriel Samoila <cosmin.samoila@nxp.com> Signed-off-by: NShengjiu Wang <shengjiu.wang@nxp.com> Acked-by: NNicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/1599112427-22038-1-git-send-email-shengjiu.wang@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>
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由 Shengjiu Wang 提交于
One data channel is one data line. From imx7ulp, the SAI IP is enhanced to support multiple data channels. If there is only two channels input and slots is 2, then enable one data channel is enough for data transfer. So enable the TCE/RCE and transmit/receive mask register according to the input channels and slots configuration. Move the data channel enablement from startup() to hw_params(). Signed-off-by: NShengjiu Wang <shengjiu.wang@nxp.com> Acked-by: NNicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/1598958068-10552-1-git-send-email-shengjiu.wang@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>
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- 24 8月, 2020 1 次提交
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由 Shengjiu Wang 提交于
Regmap initialization may return -EPROBE_DEFER for clock may not be ready, so check -EPROBE_DEFER error type before start another Regmap initialization. Signed-off-by: NShengjiu Wang <shengjiu.wang@nxp.com> Acked-by: NNicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/1598255887-1391-1-git-send-email-shengjiu.wang@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>
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- 17 8月, 2020 3 次提交
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由 Shengjiu Wang 提交于
As new function fsl_sai_dir_is_synced is included for checking if stream is synced by the opposite stream, then replace the existing synchronous checking with this new function. Signed-off-by: NShengjiu Wang <shengjiu.wang@nxp.com> Acked-by: NNicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/20200805063413.4610-4-shengjiu.wang@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>
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由 Shengjiu Wang 提交于
Tx synchronous with Rx: The RMR is the word mask register, it is used to mask any word in the frame, it is not relating to clock generation, So it is no need to be changed when Tx is going to be enabled. Rx synchronous with Tx: The TMR is the word mask register, it is used to mask any word in the frame, it is not relating to clock generation, So it is no need to be changed when Rx is going to be enabled. Signed-off-by: NShengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: NNicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/20200805063413.4610-3-shengjiu.wang@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>
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由 Shengjiu Wang 提交于
Current code enables TCSR.TE and RCSR.RE together, and disable TCSR.TE and RCSR.RE together in trigger(), which only supports one operation mode: 1. Rx synchronous with Tx: TE is last enabled and first disabled Other operation mode need to be considered also: 2. Tx synchronous with Rx: RE is last enabled and first disabled. 3. Asynchronous mode: Tx and Rx are independent. So the enable TCSR.TE and RCSR.RE sequence and the disable sequence need to be refined accordingly for #2 and #3. There is slightly against what RM recommennds with this change. For example in Rx synchronous with Tx mode, case "aplay 1.wav; arecord 2.wav" enable TE before RE. But it should be safe to do so, judging by years of testing results. Signed-off-by: NShengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: NNicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/20200805063413.4610-2-shengjiu.wang@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>
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- 01 8月, 2020 1 次提交
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由 Shengjiu Wang 提交于
The fifo_depth is 64 on i.MX8QM/i.MX8QXP, 128 on i.MX8MQ, 16 on i.MX7ULP. Original FSL_SAI_CR1_RFW_MASK value 0x1F is not suitable for these platform, the FIFO watermark mask should be updated according to the fifo_depth. Fixes: a860fac4 ("ASoC: fsl_sai: Add support for imx7ulp/imx8mq") Signed-off-by: NShengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: NFabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/1596176895-28724-1-git-send-email-shengjiu.wang@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>
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- 02 7月, 2020 1 次提交
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由 Shengjiu Wang 提交于
When there is dedicated power domain bound with device, after probing the power will be disabled, then registers are not accessible in fsl_sai_dai_probe(), so regcache only need to be enabled in end of probe() and regcache_mark_dirty should be moved to pm runtime resume callback function. Signed-off-by: NShengjiu Wang <shengjiu.wang@nxp.com> Acked-by: NNicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/1593412953-10897-1-git-send-email-shengjiu.wang@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>
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- 06 2月, 2020 1 次提交
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由 Oleksandr Suvorov 提交于
If the imx-sdma driver is built as a module, the fsl-sai device doesn't disable on probing failure, which causes the warning in the next probing: ================================================================== fsl-sai 308a0000.sai: Unbalanced pm_runtime_enable! fsl-sai 308a0000.sai: Unbalanced pm_runtime_enable! fsl-sai 308a0000.sai: Unbalanced pm_runtime_enable! fsl-sai 308a0000.sai: Unbalanced pm_runtime_enable! fsl-sai 308a0000.sai: Unbalanced pm_runtime_enable! fsl-sai 308a0000.sai: Unbalanced pm_runtime_enable! ================================================================== Disabling the device properly fixes the issue. Fixes: 812ad463 ("ASoC: fsl_sai: Add support for runtime pm") Signed-off-by: NOleksandr Suvorov <oleksandr.suvorov@toradex.com> Link: https://lore.kernel.org/r/20200205160436.3813642-1-oleksandr.suvorov@toradex.comSigned-off-by: NMark Brown <broonie@kernel.org>
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- 10 12月, 2019 1 次提交
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由 Michael Walle 提交于
The LS1028A SoC uses the same interrupt line for adjacent SAIs. Use IRQF_SHARED to be able to use these SAIs simultaneously. Signed-off-by: NMichael Walle <michael@walle.cc> Reviewed-by: NFabio Estevam <festevam@gmail.com> Acked-by: NNicolin Chen <nicoleotsuka@gmail.com> Acked-by: NDaniel Baluta <daniel.baluta@nxp.com> Link: https://lore.kernel.org/r/20191128223802.18228-1-michael@walle.ccSigned-off-by: NMark Brown <broonie@kernel.org>
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- 17 9月, 2019 1 次提交
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由 Mihai Serban 提交于
EDMA requires the period size to be multiple of maxburst. Otherwise the remaining bytes are not transferred and thus noise is produced. We can handle this issue by adding a constraint on SNDRV_PCM_HW_PARAM_PERIOD_SIZE to be multiple of tx/rx maxburst value. Signed-off-by: NMihai Serban <mihai.serban@nxp.com> Signed-off-by: NDaniel Baluta <daniel.baluta@nxp.com> Acked-by: NNicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/20190913192807.8423-2-daniel.baluta@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>
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- 13 9月, 2019 1 次提交
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由 Viorel Suman 提交于
This is to allow machine drivers to set a certain bitclk rate which might not be exactly rate * frame size. Cc: NXP Linux Team <linux-imx@nxp.com> Signed-off-by: NViorel Suman <viorel.suman@nxp.com> Signed-off-by: NDaniel Baluta <daniel.baluta@nxp.com> Acked-by: NNicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/20190830215910.31590-1-daniel.baluta@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>
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- 21 8月, 2019 1 次提交
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由 Daniel Baluta 提交于
SAI module on imx8qm features a register map similar with imx6 series (it doesn't have VERID and PARAM registers at the beginning of address spece). Also, it has one FIFO which can help up to 64 * 32 bit samples. Signed-off-by: NDaniel Baluta <daniel.baluta@nxp.com> Link: https://lore.kernel.org/r/20190814082911.665-2-daniel.baluta@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>
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- 07 8月, 2019 4 次提交
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由 Daniel Baluta 提交于
SAI module on imx7ulp/imx8m features 2 new registers (VERID and PARAM) at the beginning of register address space. On imx7ulp FIFOs can held up to 16 x 32 bit samples. On imx8mq FIFOs can held up to 128 x 32 bit samples. Signed-off-by: NDaniel Baluta <daniel.baluta@nxp.com> Acked-by: NNicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/20190806151214.6783-5-daniel.baluta@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>
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由 Daniel Baluta 提交于
New IP version introduces Version ID and Parameter registers and optionally added Timestamp feature. VERID and PARAM registers are placed at the top of registers address space and some registers are shifted according to the following table: Tx/Rx data registers and Tx/Rx FIFO registers keep their addresses, all other registers are shifted by 8. SAI Memory map is described in chapter 13.10.4.1.1 I2S Memory map of the Reference Manual [1]. In order to make as less changes as possible we attach an offset to each register offset to each changed register definition. The offset is read from each board private data. [1]https://cache.nxp.com/secured/assets/documents/en/reference-manual/IMX8MDQLQRM.pdf?__gda__=1563728701_38bea7f0f726472cc675cb141b91bec7&fileExt=.pdfSigned-off-by: NMihai Serban <mihai.serban@nxp.com> [initial coding in the NXP internal tree] Signed-off-by: NShengjiu Wang <shengjiu.wang@nxp.com> [bugfixing and cleanups] Signed-off-by: NDaniel Baluta <daniel.baluta@nxp.com> [adapted to linux-next] Acked-by: NNicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/20190806151214.6783-4-daniel.baluta@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>
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由 Daniel Baluta 提交于
Tx channel enable (TCE) / Rx channel enable (RCE) bits enable corresponding data channel for Tx/Rx operation. Because SAI supports up the 8 channels TCE/RCE occupy up the 8 bits inside TCR3/RCR3 registers we need to extend the mask to reflect this. Signed-off-by: NDaniel Baluta <daniel.baluta@nxp.com> Acked-by: NNicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/20190806151214.6783-3-daniel.baluta@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>
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由 Daniel Baluta 提交于
SAI IP supports up to 8 data lines. The configuration of supported number of data lines is decided at SoC integration time. This patch adds definitions for all related data TX/RX registers: * TDR0..7, Transmit data register * TFR0..7, Transmit FIFO register * RDR0..7, Receive data register * RFR0..7, Receive FIFO register Signed-off-by: NDaniel Baluta <daniel.baluta@nxp.com> Acked-by: NNicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/20190806151214.6783-2-daniel.baluta@nxp.comSigned-off-by: NMark Brown <broonie@kernel.org>
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- 02 8月, 2019 1 次提交
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由 Stephen Boyd 提交于
We don't need dev_err() messages when platform_get_irq() fails now that platform_get_irq() prints an error message itself when something goes wrong. Let's remove these prints with a simple semantic patch. // <smpl> @@ expression ret; struct platform_device *E; @@ ret = ( platform_get_irq(E, ...) | platform_get_irq_byname(E, ...) ); if ( \( ret < 0 \| ret <= 0 \) ) { ( -if (ret != -EPROBE_DEFER) -{ ... -dev_err(...); -... } | ... -dev_err(...); ) ... } // </smpl> While we're here, remove braces on if statements that only have one statement (manually). Cc: Liam Girdwood <lgirdwood@gmail.com> Cc: Mark Brown <broonie@kernel.org> Cc: Jaroslav Kysela <perex@perex.cz> Cc: Takashi Iwai <tiwai@suse.com> Cc: alsa-devel@alsa-project.org Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: NStephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20190730181557.90391-50-swboyd@chromium.orgSigned-off-by: NMark Brown <broonie@kernel.org>
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- 22 7月, 2019 3 次提交
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由 Lucas Stach 提交于
The regmap is only ever used to access MMIO registers, so it's fair to say that register access is fast. Signed-off-by: NLucas Stach <l.stach@pengutronix.de> Link: https://lore.kernel.org/r/20190717105156.15721-1-l.stach@pengutronix.deSigned-off-by: NMark Brown <broonie@kernel.org>
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由 Lucas Stach 提交于
The DMA request schould be triggered as soon as the FIFO has space for another burst. As different versions of the SAI block have different FIFO sizes, the watrmark level needs to be derived from version specific data. Signed-off-by: NLucas Stach <l.stach@pengutronix.de> Tested-by: NAngus Ainslie <angus@akkea.ca> Reviewed-by: NAngus Ainslie <angus@akkea.ca> Link: https://lore.kernel.org/r/20190717105635.18514-3-l.stach@pengutronix.deSigned-off-by: NMark Brown <broonie@kernel.org>
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由 Lucas Stach 提交于
New revisions of the SAI IP block have even more differences that need be taken into account by the driver. To avoid sprinking compatible checks all over the driver move the current differences into of_match_data. Signed-off-by: NLucas Stach <l.stach@pengutronix.de> Tested-by: NAngus Ainslie <angus@akkea.ca> Reviewed-by: NAngus Ainslie <angus@akkea.ca> Reviewed-by: NDaniel Baluta <daniel.baluta@nxp.com> Link: https://lore.kernel.org/r/20190717105635.18514-2-l.stach@pengutronix.deSigned-off-by: NMark Brown <broonie@kernel.org>
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- 08 5月, 2019 1 次提交
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由 Shengjiu Wang 提交于
Turn off/on clocks when device enters suspend/resume. This can help saving power. As a further optimization, we turn off/on mclk only when SAI is in master mode because otherwise mclk is externally provided. Signed-off-by: NShengjiu Wang <shengjiu.wang@nxp.com> Signed-off-by: NDaniel Baluta <daniel.baluta@nxp.com> Reviewed-by: NViorel Suman <viorel.suman@nxp.com> Acked-by: NNicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 26 4月, 2019 3 次提交
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由 Nicolin Chen 提交于
Build warning being reported: sound/soc/fsl/fsl_sai.c: In function 'fsl_sai_remove': sound/soc/fsl/fsl_sai.c:921:1: warning: no return statement in function returning non-void [-Wreturn-type] So this patch just adds a "return 0" to fix it. Fixes: 812ad463 ("ASoC: fsl_sai: Add support for runtime pm") Reported-by: NStephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: NNicolin Chen <nicoleotsuka@gmail.com> Reviewed-by: NDaniel Baluta <daniel.baluta@nxp.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Daniel Baluta 提交于
Basically the same actions as for system PM, so make use of pm_runtime_force_suspend/pm_runtime_force_resume. Signed-off-by: NShengjiu Wang <shengjiu.wang@nxp.com> Signed-off-by: NDaniel Baluta <daniel.baluta@nxp.com> Acked-by: NNicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Daniel Baluta 提交于
is_slave_mode defaults to false because sai structure that contains it is kzalloc'ed. Anyhow, if we decide to set the following configuration SAI slave -> SAI master, is_slave_mode will remain set on true although SAI being master it should be set to false. Fix this by updating is_slave_mode for each call of fsl_sai_set_dai_fmt. Signed-off-by: NDaniel Baluta <daniel.baluta@nxp.com> Acked-by: NNicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 19 1月, 2019 1 次提交
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由 Shengjiu Wang 提交于
When stopping audio, ASoC will first stop DMA then CPU DAI. Sometimes there is a delay between DMA stop and CPU DAI stop, which triggers an underrun error. Now, because of the delay introduced by dev_err another underrun error will occur causing a vicious circle making impossible to stop CPU DAI. Signed-off-by: NShengjiu Wang <shengjiu.wang@nxp.com> Signed-off-by: NDaniel Baluta <daniel.baluta@nxp.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 03 5月, 2018 1 次提交
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由 Fabio Estevam 提交于
Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 14 2月, 2017 1 次提交
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由 Alexandre Belloni 提交于
The FSL SAI can support up to 32 channels using TDM. Report that value so they can actually be used. Tested using 8 channels. Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: NNicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 17 8月, 2016 1 次提交
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由 Fabio Estevam 提交于
The 'np' variable is already assigned to 'pdev->dev.of_node', so use it to improve readability. No functional change. Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 05 5月, 2016 2 次提交
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由 Fabio Estevam 提交于
On mx6ul the General Purpose Register 1 (GPR1) contains the following bits for configuring the direction of the SAI MCLKs: SAI1_MCLK_DIR, SAI2_MCLK_DIR, SAI3_MCLK_DIR Introduce the "fsl,sai-mclk-direction-output" optional property to allow configuring the SAI_MCLK outputs. Tested on a imx6ul-evk board. Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com> Acked-by: NNicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Fabio Estevam 提交于
MX6UL may need to configure the General Purpose Register 1 (GPR1), so it is better to add a new compatible string to differentiate. Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com> Acked-by: NNicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 23 1月, 2016 1 次提交
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由 Xiubo Li 提交于
Since msleep() will sleep longer than intended time for values less than 20ms, this patch allows the use of usleep_range for just 1ms. usleep_range is a finer precision implementation of msleep and is designed to be a drop-in replacement for udelay where a precise sleep/busy-wait is unnecessary. More details see Documentation/timers/timers-howto.txt. Signed-off-by: NXiubo Li <lixiubo@cmss.chinamobile.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 18 12月, 2015 1 次提交
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由 Zidan Wang 提交于
After several open/close sai test with ctrl+c, there will be I/O error. The SAI can't work anymore, can't recover. There will be no frame clock. With adding the software reset in trigger stop, the issue can be fixed. This is a hardware bug/errata and reset is the only option. According to the reference manual, the software reset doesn't reset any control register but only internal hardware logics such as bit clock generator, status flags, and FIFO pointers. (Our purpose is just to reset the clock generator while the software reset is the only way to do that.) Since slave mode doesn't use the clock generator, only apply the reset procedure to the master mode. For asynchronous mode, TX will not be reset when RX is still running. In this case, i can't reproduce this issue. Signed-off-by: NZidan Wang <zidan.wang@freescale.com> Acked-by: NNicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 25 11月, 2015 2 次提交
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由 Zidan Wang 提交于
using params_width function to simplify code. Signed-off-by: NZidan Wang <zidan.wang@freescale.com> Acked-by: NNicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Zidan Wang 提交于
Add tdm slots operation support. If tdm slots and slot width have been configured in machine driver, we should use these values. Otherwise, using relevant channels and word length to set slots and slot width. SAI will generate BCLK depends on sample rate, slots and slot width. And there may be unused BCLK cycles before each LRCLK transition. Signed-off-by: NZidan Wang <zidan.wang@freescale.com> Acked-by: NNicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 18 11月, 2015 2 次提交
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由 Zidan Wang 提交于
For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4), RCR5(TCR5) and RMR(TMR) for playback(capture), or there will be sync error sometimes. Signed-off-by: NZidan Wang <zidan.wang@freescale.com> Acked-by: NNicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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由 Zidan Wang 提交于
In fsl_sai_set_bclk function, we should not set bclk for Tx/Rx Synchronous with another SAI mode. Signed-off-by: NZidan Wang <zidan.wang@freescale.com> Acked-by: NNicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 16 11月, 2015 1 次提交
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由 Zidan Wang 提交于
FSL_SAI_TDR register is writable and not readable. According to regmap_volatile() function, if FSL_SAI_TDR want to be volatile, it should be readable. So we should remove FSL_SAI_TDR from volatile register list. If the flat cache don't have default register map, when do regcache_sync operation, the non volatile and writable registers will be synchronised to 0. FSL_SAI_TDR reigster will be written a 0 and cause channel swap. So add default register map for flat cache, and such register will not be written. Signed-off-by: NZidan Wang <zidan.wang@freescale.com> Acked-by: NNicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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