1. 15 3月, 2016 15 次提交
    • S
      net: thunderx: Adjust nicvf structure to reduce cache misses · 1d368790
      Sunil Goutham 提交于
      Adjusted nicvf structure such that all elements used in hot
      path like napi, xmit e.t.c fall into same cache line. This reduced
      no of cache misses and resulted in ~2% increase in no of packets
      handled on a core.
      
      Also modified elements with :1 notation to boolean, to be
      consistent with other element definitions.
      Signed-off-by: NSunil Goutham <sgoutham@cavium.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      1d368790
    • S
      net: thunderx: Set recevie buffer page usage count in bulk · 5c2e26f6
      Sunil Goutham 提交于
      Instead of calling get_page() for every receive buffer carved out
      of page, set page's usage count at the end, to reduce no of atomic
      calls.
      Signed-off-by: NSunil Goutham <sgoutham@cavium.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      5c2e26f6
    • R
      tipc: make sure IPv6 header fits in skb headroom · 9bd160bf
      Richard Alpe 提交于
      Expand headroom further in order to be able to fit the larger IPv6
      header. Prior to this patch this caused a skb under panic for certain
      tipc packets when using IPv6 UDP bearer(s).
      Signed-off-by: NRichard Alpe <richard.alpe@ericsson.com>
      Acked-by: NJon Maloy <jon.maloy@ericsson.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      9bd160bf
    • D
      Merge branch 'mvneta-hwbm' · c9214f50
      David S. Miller 提交于
      Gregory CLEMENT says:
      
      ====================
      API set for HW Buffer management
      
      This is the sixth version of the API set for HW Buffer management (that was
      initially submitted here:
      http://thread.gmane.org/gmane.linux.kernel/2125152).
      
      This version is just a rebasing onto the last net-next. I also added
      the Tested-by flag from Sebastian Careba : "The patch set applies
      successfully and it works well, no more Samba issues any longer".
      
      For the record in the previous versions I made the following changes:
      v4 -> v5:
      - Add a field with the size of the buffer of the pool was added. It
        then allow to fix some misused size in the mvneta_bm code when using
        the new framework.
      
      - Add a new patch from Marcin for sram allowing to require
        non-bufferable access to the memory. It was needed for the hardware
        buffer management of the mvneta.
      
      - Fix the build issue notified by the 0-day builder when building the
        drivers as module.
      
      v3 -> v4
      - Fix build issue when HWBM is not selected
      
      v2 -> v3
      - Make a HWBM and a SWBM version of the mvneta_rx() function in order
        to reduce the the conditional code. Kept a condition inside the
        mvneta_poll because specializing this function would have means
        duplicating 95% of the code.
      
      - Put back the register_netdev() call at the end of the mvneta_probe()
        function. In order to have a unique ID for each port, just used a
        global variable in the driver.
      
      - Added a fix from Marcin in the "net: mvneta: bm: add support for
        hardware buffer management" patch: "when dropping packets, only
        buffer pointers passed from BM to descriptors have to be returned to
        the pool. In submitted version after closing the port and
        mvneta_rxq_deinit(), it was very likely that a lot of fake buffers
        are added to the pool, because all descriptors took part in
        iteration."
      
      - Removed the select MVNETA_BM from the Kconfig, it will let the user
        the choice to use not use it if they want.
      
      v1 -> v2
      - The hardware buffer management helpers are no more built by default
        and now depend on a hidden config symbol which has to be selected
        by the driver if needed
      - The hwbm_pool_refill() and hwbm_pool_add() now receive a gfp_t as
        argument allowing the caller to specify the flag it needs.
      - buf_num is now tested to ensure there is no wrapping
      - A spinlock has been added to protect the hwbm_pool_add() function in
        SMP or irq context.
      - used pr_warn instead of pr_debug in case of errors.
      - fixed the mvneta implementation by returning the buffer to the pool
        at various place instead of ignoring it.
      - Squashed "bus: mvenus-mbus: Fix size test for
         mvebu_mbus_get_dram_win_info" into bus: mvebu-mbus: provide api for
         obtaining IO and DRAM window information.
      - Added my signed-otf-by on all the patches as submitter of the series.
      - Renamed the dts patches with the pattern "ARM: dts: platform:"
      - Removed the patch "ARM: mvebu: enable SRAM support in
        mvebu_v7_defconfig" of this series and already applied it
      - Modified the order of the patches.
      
      In order to ease the test the branch mvneta-BM-framework-v6 is
      available at git@github.com:MISL-EBU-System-SW/mainline-public.git.
      ====================
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      c9214f50
    • G
      net: mvneta: Use the new hwbm framework · baa11ebc
      Gregory CLEMENT 提交于
      Now that the hardware buffer management framework had been introduced,
      let's use it.
      Tested-by: NSebastian Careba <nitroshift@yahoo.com>
      Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      baa11ebc
    • G
      net: add a hardware buffer management helper API · 8cb2d8bf
      Gregory CLEMENT 提交于
      This basic implementation allows to share code between driver using
      hardware buffer management. As the code is hardware agnostic, there is
      few helpers, most of the optimization brought by the an HW BM has to be
      done at driver level.
      Tested-by: NSebastian Careba <nitroshift@yahoo.com>
      Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      8cb2d8bf
    • M
      net: mvneta: bm: add support for hardware buffer management · dc35a10f
      Marcin Wojtas 提交于
      Buffer manager (BM) is a dedicated hardware unit that can be used by all
      ethernet ports of Armada XP and 38x SoC's. It allows to offload CPU on RX
      path by sparing DRAM access on refilling buffer pool, hardware-based
      filling of descriptor ring data and better memory utilization due to HW
      arbitration for using 'short' pools for small packets.
      
      Tests performed with A388 SoC working as a network bridge between two
      packet generators showed increase of maximum processed 64B packets by
      ~20k (~555k packets with BM enabled vs ~535 packets without BM). Also
      when pushing 1500B-packets with a line rate achieved, CPU load decreased
      from around 25% without BM to 20% with BM.
      
      BM comprise up to 4 buffer pointers' (BP) rings kept in DRAM, which
      are called external BP pools - BPPE. Allocating and releasing buffer
      pointers (BP) to/from BPPE is performed indirectly by write/read access
      to a dedicated internal SRAM, where internal BP pools (BPPI) are placed.
      BM hardware controls status of BPPE automatically, as well as assigning
      proper buffers to RX descriptors. For more details please refer to
      Functional Specification of Armada XP or 38x SoC.
      
      In order to enable support for a separate hardware block, common for all
      ports, a new driver has to be implemented ('mvneta_bm'). It provides
      initialization sequence of address space, clocks, registers, SRAM,
      empty pools' structures and also obtaining optional configuration
      from DT (please refer to device tree binding documentation). mvneta_bm
      exposes also a necessary API to mvneta driver, as well as a dedicated
      structure with BM information (bm_priv), whose presence is used as a
      flag notifying of BM usage by port. It has to be ensured that mvneta_bm
      probe is executed prior to the ones in ports' driver. In case BM is not
      used or its probe fails, mvneta falls back to use software buffer
      management.
      
      A sequence executed in mvneta_probe function is modified in order to have
      an access to needed resources before possible port's BM initialization is
      done. According to port-pools mapping provided by DT appropriate registers
      are configured and the buffer pools are filled. RX path is modified
      accordingly. Becaues the hardware allows a wide variety of configuration
      options, following assumptions are made:
      * using BM mechanisms can be selectively disabled/enabled basing
        on DT configuration among the ports
      * 'long' pool's single buffer size is tied to port's MTU
      * using 'long' pool by port is obligatory and it cannot be shared
      * using 'short' pool for smaller packets is optional
      * one 'short' pool can be shared among all ports
      
      This commit enables hardware buffer management operation cooperating with
      existing mvneta driver. New device tree binding documentation is added and
      the one of mvneta is updated accordingly.
      
      [gregory.clement@free-electrons.com: removed the suspend/resume part]
      Signed-off-by: NMarcin Wojtas <mw@semihalf.com>
      Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      dc35a10f
    • M
      bus: mvebu-mbus: provide api for obtaining IO and DRAM window information · f2900ace
      Marcin Wojtas 提交于
      This commit enables finding appropriate mbus window and obtaining its
      target id and attribute for given physical address in two separate
      routines, both for IO and DRAM windows. This functionality
      is needed for Armada XP/38x Network Controller's Buffer Manager and
      PnC configuration.
      
      [gregory.clement@free-electrons.com: Fix size test for
      mvebu_mbus_get_dram_win_info]
      Signed-off-by: NMarcin Wojtas <mw@semihalf.com>
      [DRAM window information reference in LKv3.10]
      Signed-off-by: NEvan Wang <xswang@marvell.com>
      Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      f2900ace
    • G
      ARM: dts: armada-xp-openblocks-ax3-4: Add BM support · 293fdc24
      Gregory CLEMENT 提交于
      Allow Openblock AX3 using hardware buffer management with mvneta.
      Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      293fdc24
    • M
      ARM: dts: armada-xp: enable buffer manager support on Armada XP boards · 9dd7a57e
      Marcin Wojtas 提交于
      Since mvneta driver supports using hardware buffer management (BM), in
      order to use it, board files have to be adjusted accordingly. This commit
      enables BM on AXP-DB and AXP-GP in same manner - because number of ports
      on those boards is the same as number of possible pools, each port is
      supposed to use single pool for all kind of packets.
      
      Moreover appropriate entry is added to 'soc' node ranges, as well as "okay"
      status for 'bm' and 'bm-bppi' (internal SRAM) nodes.
      Signed-off-by: NMarcin Wojtas <mw@semihalf.com>
      Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      9dd7a57e
    • M
      ARM: dts: armada-xp: add buffer manager nodes · ebae1376
      Marcin Wojtas 提交于
      Armada XP network controller supports hardware buffer management (BM).
      Since it is now enabled in mvneta driver, appropriate nodes can be added
      to armada-xp.dtsi - for the actual common BM unit (bm@c0000) and its
      internal SRAM (bm-bppi), which is used for indirect access to buffer
      pointer ring residing in DRAM.
      
      Pools - ports mapping, bm-bppi entry in 'soc' node's ranges and optional
      parameters are supposed to be set in board files.
      Signed-off-by: NMarcin Wojtas <mw@semihalf.com>
      Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      ebae1376
    • M
      ARM: dts: armada-38x: enable buffer manager support on Armada 38x boards · c49e99c2
      Marcin Wojtas 提交于
      Since mvneta driver supports using hardware buffer management (BM), in
      order to use it, board files have to be adjusted accordingly. This commit
      enables BM on:
      * A385-DB-AP - each port has its own pool for long and common pool for
      short packets,
      * A388-ClearFog - same as above,
      * A388-DB - to each port unique 'short' and 'long' pools are mapped,
      * A388-GP - same as above.
      
      Moreover appropriate entry is added to 'soc' node ranges, as well as "okay"
      status for 'bm' and 'bm-bppi' (internal SRAM) nodes.
      
      [gregory.clement@free-electrons.com: add suppport for the ClearFog board]
      Signed-off-by: NMarcin Wojtas <mw@semihalf.com>
      Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
      Acked-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      c49e99c2
    • M
      ARM: dts: armada-38x: add buffer manager nodes · 4a547a5a
      Marcin Wojtas 提交于
      Armada 38x network controller supports hardware buffer management (BM).
      Since it is now enabled in mvneta driver, appropriate nodes can be added
      to armada-38x.dtsi - for the actual common BM unit (bm@c8000) and its
      internal SRAM (bm-bppi), which is used for indirect access to buffer
      pointer ring residing in DRAM.
      
      Pools - ports mapping, bm-bppi entry in 'soc' node's ranges and optional
      parameters are supposed to be set in board files.
      Signed-off-by: NMarcin Wojtas <mw@semihalf.com>
      Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      4a547a5a
    • M
      misc: sram: add optional ioremap without write combining · eb43e023
      Marcin Wojtas 提交于
      Some SRAM users may require non-bufferable access to the memory, which is
      impossible, because devm_ioremap_wc() is used for setting sram->virt_base.
      
      This commit adds optional flag 'no-memory-wc', which allow to choose remap
      method, using DT property. Documentation is updated accordingly.
      Signed-off-by: NMarcin Wojtas <mw@semihalf.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      eb43e023
    • D
      Merge tag 'wireless-drivers-next-for-davem-2016-03-14' of... · d3bf9b19
      David S. Miller 提交于
      Merge tag 'wireless-drivers-next-for-davem-2016-03-14' of git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/wireless-drivers-next
      
      Kalle Valo says:
      
      ====================
      wireless-drivers patches for 4.6
      
      Major changes:
      
      rtl8xxxu
      
      * add 8723bu support
      
      wl18xx
      
      * add radar_debug_mode debugfs file for DFS testing
      ====================
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      d3bf9b19
  2. 14 3月, 2016 25 次提交