1. 02 3月, 2012 1 次提交
  2. 13 2月, 2012 1 次提交
    • F
      usb: dwc3: convert TRBs into bitshifts · f6bafc6a
      Felipe Balbi 提交于
      this will get rid of a useless memcpy on
      IRQ handling, thus improving driver performance.
      
      Tested with OMAP5430 running g_mass_storage on
      SuperSpeed and HighSpeed.
      
      Note that we are removing the little endian access
      of the TRB and all accesses will be in System endianness,
      if there happens to be a system in BE, bit 12 of GSBUSCFG0
      should be set so that HW does byte invariant BE accesses
      when fetching TRBs.
      Signed-off-by: NFelipe Balbi <balbi@ti.com>
      f6bafc6a
  3. 10 2月, 2012 1 次提交
    • G
      usb: dwc3: ep0: fix SetFeature(TEST) · 3b637367
      Gerard Cauvy 提交于
      When host requests us to enter a test mode,
      we cannot directly enter the test mode before
      Status Phase is completed, otherwise the core
      will never be able to deliver the Status ZLP
      to host, because it has already entered the
      requested Test Mode.
      
      In order to fix the error, we move the actual
      start of Test Mode right after we receive
      Transfer Complete event of the status phase.
      Signed-off-by: NGerard Cauvy <g-cauvy1@ti.com>
      Signed-off-by: NFelipe Balbi <balbi@ti.com>
      3b637367
  4. 06 2月, 2012 3 次提交
  5. 12 12月, 2011 15 次提交
  6. 05 10月, 2011 5 次提交
  7. 09 9月, 2011 11 次提交
  8. 23 8月, 2011 1 次提交
    • F
      usb: Introduce DesignWare USB3 DRD Driver · 72246da4
      Felipe Balbi 提交于
      The DesignWare USB3 is a highly
      configurable IP Core which can be
      instantiated as Dual-Role Device (DRD),
      Peripheral Only and Host Only (XHCI)
      configurations.
      
      Several other parameters can be configured
      like amount of FIFO space, amount of TX and
      RX endpoints, amount of Host Interrupters,
      etc.
      
      The current driver has been validated with
      a virtual model of version 1.73a of that core
      and with an FPGA burned with version 1.83a
      of the DRD core. We have support for PCIe
      bus, which is used on FPGA prototyping, and
      for the OMAP5, more adaptation (or glue)
      layers can be easily added and the driver
      is half prepared to handle any possible
      configuration the HW engineer has chosen
      considering we have the information on
      one of the GHWPARAMS registers to do
      runtime checking of certain features.
      
      More runtime checks can, and should, be added
      in order to make this driver even more flexible
      with regards to number of endpoints, FIFO sizes,
      transfer types, etc.
      
      While this supports only the device side, for
      now, we will add support for Host side (xHCI -
      see the updated series Sebastian has sent [1])
      and OTG after we have it all stabilized.
      
      [1] http://marc.info/?l=linux-usb&m=131341992020339&w=2Signed-off-by: NFelipe Balbi <balbi@ti.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      72246da4