1. 19 5月, 2018 4 次提交
    • D
      Merge branch 'bpf-nfp-shift-insns' · 1cb61381
      Daniel Borkmann 提交于
      Jiong Wang says:
      
      ====================
      NFP eBPF JIT is missing logic indirect shifts (both left and right) and
      arithmetic right shift (both indirect shift and shift by constant).
      
      This patch adds support for them.
      
      For indirect shifts, shift amount is not specified as constant, NFP needs
      to get the shift amount through the low 5 bits of source A operand in
      PREV_ALU, therefore extra instructions are needed compared with shifts by
      constants.
      
      Because NFP is 32-bit, so we are using register pair for 64-bit shifts and
      therefore would need different instruction sequences depending on whether
      shift amount is less than 32 or not.
      
      NFP branch-on-bit-test instruction emitter is added by this patch set and
      is used for efficient runtime check on shift amount. We'd think the shift
      amount is less than 32 if bit 5 is clear and greater or equal then 32
      otherwise. Shift amount is greater than or equal to 64 will result in
      undefined behavior.
      
      This patch also use range info to avoid generating unnecessary runtime code
      if we are certain shift amount is less than 32 or not.
      ====================
      Signed-off-by: NDaniel Borkmann <daniel@iogearbox.net>
      1cb61381
    • J
      nfp: bpf: support arithmetic indirect right shift (BPF_ARSH | BPF_X) · c217abcc
      Jiong Wang 提交于
      Code logic is similar with arithmetic right shift by constant, and NFP
      get indirect shift amount through source A operand of PREV_ALU.
      
      It is possible to fall back to logic right shift if the MSB is known to be
      zero from range info, however there is no benefit to do this given logic
      indirect right shift use the same number and cycle of instruction sequence.
      
      Suppose the MSB of regX is the bit we want to replicate to fill in all the
      vacant positions, and regY contains the shift amount, then we could use
      single instruction to set up both.
      
        [alu, --, regY, OR, regX]
      
        --
        NOTE: the PREV_ALU result doesn't need to write to any destination
              register.
      Signed-off-by: NJiong Wang <jiong.wang@netronome.com>
      Reviewed-by: NJakub Kicinski <jakub.kicinski@netronome.com>
      Signed-off-by: NDaniel Borkmann <daniel@iogearbox.net>
      c217abcc
    • J
      nfp: bpf: support arithmetic right shift by constant (BPF_ARSH | BPF_K) · f43d0f17
      Jiong Wang 提交于
      Code logic is similar with logic right shift except we also need to set
      PREV_ALU result properly, the MSB of which is the bit that will be
      replicated to fill in all the vacant positions.
      Signed-off-by: NJiong Wang <jiong.wang@netronome.com>
      Reviewed-by: NJakub Kicinski <jakub.kicinski@netronome.com>
      Signed-off-by: NDaniel Borkmann <daniel@iogearbox.net>
      f43d0f17
    • J
      nfp: bpf: support logic indirect shifts (BPF_[L|R]SH | BPF_X) · 991f5b36
      Jiong Wang 提交于
      For indirect shifts, shift amount is not specified as constant, NFP needs
      to get the shift amount through the low 5 bits of source A operand in
      PREV_ALU, therefore extra instructions are needed compared with shifts by
      constants.
      
      Because NFP is 32-bit, so we are using register pair for 64-bit shifts and
      therefore would need different instruction sequences depending on whether
      shift amount is less than 32 or not.
      
      NFP branch-on-bit-test instruction emitter is added by this patch and is
      used for efficient runtime check on shift amount. We'd think the shift
      amount is less than 32 if bit 5 is clear and greater or equal than 32
      otherwise. Shift amount is greater than or equal to 64 will result in
      undefined behavior.
      
      This patch also use range info to avoid generating unnecessary runtime code
      if we are certain shift amount is less than 32 or not.
      Signed-off-by: NJiong Wang <jiong.wang@netronome.com>
      Reviewed-by: NJakub Kicinski <jakub.kicinski@netronome.com>
      Signed-off-by: NDaniel Borkmann <daniel@iogearbox.net>
      991f5b36
  2. 18 5月, 2018 7 次提交
  3. 17 5月, 2018 29 次提交