This patch added bf60x to current blackfin kernel framework.
Signed-off-by: NBob Liu <lliubbo@gmail.com>

This patch fix below compile error:
"bfin-uclinux-ld: L1 data A overflow!"

It is due to the recent lib/gen_crc32table.c change:
46c5801e
crc32: bolt on crc32c

it added 8KiB more data to __cacheline_aligned which cause blackfin L1 data
cache overflow.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>
Signed-off-by: NBob Liu <lliubbo@gmail.com>

ARCH_HAS_NMI_WATCHDOG is a macro defined by arch, but config
HARDLOCKUP_DETECTOR depends on it.  This is wrong, ARCH_HAS_NMI_WATCHDOG
has to be a Kconfig config, and arch's need it should select it
explicitly.
Signed-off-by: NWANG Cong <xiyou.wangcong@gmail.com>
Acked-by: NDon Zickus <dzickus@redhat.com>
Acked-by: NMike Frysinger <vapier@gentoo.org>
Cc: David Howells <dhowells@redhat.com>
Cc: David Miller <davem@davemloft.net>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Signed-off-by: NPaul Bolle <pebolle@tiscali.nl>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

For now, this only supports gptimers.  Support for dedicated PWM devices
as found on newer parts to come.
Signed-off-by: NMichael Hennerich <michael.hennerich@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

By the previous style change, CONFIG_GENERIC_FIND_NEXT_BIT,
CONFIG_GENERIC_FIND_BIT_LE, and CONFIG_GENERIC_FIND_LAST_BIT are not used
to test for existence of find bitops anymore.
Signed-off-by: NAkinobu Mita <akinobu.mita@gmail.com>
Acked-by: NGreg Ungerer <gerg@uclinux.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

All chips converted.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

In order to safely work around anomaly 05000491, we have to execute IFLUSH
from L1 instruction sram.  The trouble with multi-core systems is that all
L1 sram is visible only to the active core.  So we can't just place the
functions into L1 and call it directly.  We need to setup a jump table and
place the entry point in external memory.  This will call the right func
based on the active core.

In the process, convert from the manual relocation of a small bit of code
into Core B's L1 to the more general framework we already have in place
for loading arbitrary pieces of code into L1.
Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

We need to place icache flush funcs into L1 inst sram to work around a
hardware anomaly.  But this currently breaks SMP support as the L1 inst
sram is per-core and cannot be called directly.  So in preparation for
making that work, split the two options.

Further, split out the SMP depend so that we can allow some for SMP.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

No functional change.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Cc: Mike Frysinger <vapier@gentoo.org>

All architectures are finally converted. Remove the cruft.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Cc: Richard Henderson <rth@twiddle.net>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: David Howells <dhowells@redhat.com>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Greg Ungerer <gerg@uclinux.org>
Cc: Michal Simek <monstr@monstr.eu>
Acked-by: NDavid Howells <dhowells@redhat.com>
Cc: Kyle McMartin <kyle@mcmartin.ca>
Acked-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Chen Liqin <liqin.chen@sunplusct.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Chris Metcalf <cmetcalf@tilera.com>
Cc: Jeff Dike <jdike@addtoit.com>

Different arches use different names, so make sure we define both so
common code (like MTD_XIP) "just works".
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMichael Hennerich <michael.hennerich@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NArnaud Lacombe <lacombar@gmail.com>
Reviewed-by: NSam Ravnborg <sam@ravnborg.org>
Reviewed-by: NMichal Marek <mmarek@suse.cz>

MEM_GENERIC_BOARD depends on GENERIC_BOARD, but this flag was removed
in 4f25eb85, therefore all references
to it from the source can be removed.
Signed-off-by: NChristian Dietrich <qy03fugy@stud.informatik.uni-erlangen.de>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Anomaly 05000491 says that IFLUSH cannot have certain types of memory
stalls triggered before it has completed in order to function correctly.
One such condition is that it be in L1 instruction.  So add a config
option to move it there, default it to on, and throw up a warning when
it is turned off and this anomaly exists.

Since the anomaly should be worked around, we can drop the older method
of calling IFLUSH multiple times.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>
Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>

Now that all arches have been converted over to use generic time via
clocksources or arch_gettimeoffset(), we can remove the GENERIC_TIME
config option and simplify the generic code.
Signed-off-by: NJohn Stultz <johnstul@us.ibm.com>
LKML-Reference: <1279068988-21864-4-git-send-email-johnstul@us.ibm.com>
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

Reported-by: NChristoph Egger <siccegge@cs.fau.de>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Since 'extern inline' doesn't work correctly in the context of the Linux
kernel (too many overriding defines), move the string functions to normal
lib/ assembly files (like the existing mem funcs).  This avoids the forced
inline all over the kernel and allows us to place them constantly in L1.

This also avoids some module failures when gcc inserts calls to string
functions but the kernel build system doesn't fully consult the library
archives.
Signed-off-by: NRobin Getz <robin.getz@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

This patch removes a custom GPIO wakeup API which allowed GPIOs to act
as wakeup sources, which are not configured as Interrupts.
This API is a leftover from the time before irq_wake was established.
From now on people must use enable_irq_wake(GPIO_IRQx) and the GPIO in
question needs to be configured as Interrupt.
Signed-off-by: NMichael Hennerich <michael.hennerich@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NGraf Yang <graf.yang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NBarry Song <barry.song@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NGraf Yang <graf.yang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

SMP systems require per-cpu local clock event devices in order to enable
HRT support.  One a BF561, we can use local core timer for this purpose.
Originally, there was one global core-timer clock event device set up for
core A.

To accomplish this feat, we need to split the gptimer0/core timer logic
so that each is a standalone clock event.  There is no requirement that
we only have one clock event source anyways.  Once we have this, we just
define per-cpu clock event devices for each local core timer.
Signed-off-by: NYi Li <yi.li@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMichael Hennerich <michael.hennerich@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The option already exists for everyone in init/Kconfig.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The current Blackfin SMP code relies on the legacy cpu area code, so
select it until we port things to the newer code.
Signed-off-by: NGraf Yang <graf.yang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMichael Hennerich <michael.hennerich@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The next commit will require the use of MODULE_SYMBOL_PREFIX in
.tmp_exports-asm.S.  Currently it is mixed in with C structure
definitions in "asm/module.h".  Move the definition of this arch option
into Kconfig, so it can be easily accessed by any code.

This also lets modpost.c use the same definition.  Previously modpost
relied on a hardcoded list of architectures in mk_elfconfig.c.

A build test for blackfin, one of the two MODULE_SYMBOL_PREFIX archs,
showed the generated code was unchanged.  vmlinux was identical save
for build ids, and an apparently randomized suffix on a single "__key"
symbol in the kallsyms data).
Signed-off-by: NAlan Jenkins <alan-jenkins@tuffmail.co.uk>
Acked-by: Mike Frysinger <vapier@gentoo.org> (blackfin)
CC: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: NRusty Russell <rusty@rustcorp.com.au>

When working with 8 meg systems, forcing a 1 meg DMA chunk heavily cuts
into the available resources.  So support smaller chunks to better cover
needs for these systems.
Signed-off-by: NBarry Song <barry.song@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

While we're moving the BF54x code, have the BF54xM variants select the
normal BF54x values so that the rest of the Kconfig tree doesn't need to
check the BF54xM variant everytime it wants to check the BF54x.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>