- 19 10月, 2017 1 次提交
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由 Linus Walleij 提交于
The build robot is complaining on Blackfin: drivers/pinctrl/pinctrl-adi2.c: In function 'port_setup': >> drivers/pinctrl/pinctrl-adi2.c:221:21: error: dereferencing pointer to incomplete type 'struct gpio_port_t' writew(readw(®s->port_fer) & ~BIT(offset), ^~ drivers/pinctrl/pinctrl-adi2.c: In function 'adi_gpio_ack_irq': >> drivers/pinctrl/pinctrl-adi2.c:266:18: error: dereferencing pointer to incomplete type 'struct bfin_pint_regs' if (readl(®s->invert_set) & pintbit) ^~ It seems the driver need to include <asm/gpio.h> and <asm/irq.h> to compile. The Blackfin architecture was re-defining the Kconfig PINCTRL symbol which is not OK, so replaced this with PINCTRL_BLACKFIN_ADI2 which selects PINCTRL and PINCTRL_ADI2 just like most arches do. Further, the old GPIO driver symbol GPIO_ADI was possible to select at the same time as selecting PINCTRL. This was not working because the arch-local <asm/gpio.h> header contains an explicit #ifndef PINCTRL clause making compilation break if you combine them. The same is true for DEBUG_MMRS. Make sure the ADI2 pinctrl driver is not selected at the same time as the old GPIO implementation. (This should be converted to use gpiolib or pincontrol and move to drivers/...) Also make sure the old GPIO_ADI driver or DEBUG_MMRS is not selected at the same time as the new PINCTRL implementation, and only make PINCTRL_ADI2 selectable for the Blackfin families that actually have it. This way it is still possible to add e.g. I2C-based pin control expanders on the Blackfin. Cc: Steven Miao <realmz6@gmail.com> Cc: Huanhuan Feng <huanhuan.feng@analog.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 17 10月, 2017 1 次提交
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由 Jerome Brunet 提交于
When meson pinctrl is enabled, all meson platforms pinctrl drivers are built in the kernel, with a significant amount of data. This leads to situation where pinctrl drivers targeting an architecture are also compiled and shipped on another one (ex: meson8 - ARM - compiled and shipped on ARM64 builds). This is a waste of memory we can easily avoid. This change makes 4 pinctrl drivers (1 per SoC) out the original single driver, allowing to compile and ship only the ones required. Reviewed-by: NNeil Armstrong <narmstrong@baylibre.com> Reviewed-by: NKevin Hilman <khilman@baylibre.com> Signed-off-by: NJerome Brunet <jbrunet@baylibre.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 12 10月, 2017 1 次提交
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由 Linus Walleij 提交于
Instead of depends on GPIOLIB and having to run around in Kconfig menus looking for why your device is not available, simply select it from the pin control drivers that need it. The Kconfig for GPIOLIB is improved, selectable and this should "just work". Cc: Phil Reid <preid@electromag.com.au> Cc: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Cc: Peter Rosin <peda@axentia.se> Cc: Andrey Smirnov <andrew.smirnov@gmail.com> Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 11 10月, 2017 1 次提交
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由 Phil Reid 提交于
This allows PINCTRL to be selected manually to allow enabling of the mcp23s08 i2c/spi gpio driver. Which is not platform specific. Signed-off-by: NPhil Reid <preid@electromag.com.au> Reviewed-by: NSebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 31 8月, 2017 1 次提交
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由 Baolin Wang 提交于
This patch adds the pin control driver for Spreadtrum SC9860 platform. Signed-off-by: NBaolin Wang <baolin.wang@spreadtrum.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 21 8月, 2017 1 次提交
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由 Joseph Chen 提交于
RK805 is one of Rockchip PMICs family, it has 2 output only GPIOs. This driver is also designed for other Rockchip PMICs to expend. Different PMIC maybe have different pin features, for example, RK816 has one pin which can be used for TS or GPIO(input/out). The mainly difference between PMICs pins are pinmux, direction and output value, that is 'struct rk805_pin_config'. Signed-off-by: NJoseph Chen <chenjh@rock-chips.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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- 14 8月, 2017 1 次提交
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由 Linus Walleij 提交于
This adds a pin control (only multiplexing) driver for the Gemini SoC so we can sort out this complex platform in an orderly manner. This driver will detect the chip/package version as SL3512 or SL3516 (also known as CS3512 and CS3516 etc) and register the apropriate pin set. Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 23 6月, 2017 1 次提交
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由 Jacopo Mondi 提交于
Add combined gpio and pin controller driver for Renesas RZ/A1 r7s72100 SoC. Signed-off-by: NJacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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- 31 5月, 2017 1 次提交
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由 Arnd Bergmann 提交于
With "SPI_MASTER=y && I2C=m", we can build mcp23s08 as a built-in driver, which then results in a link failure: drivers/pinctrl/built-in.o: In function `mcp23s08_probe_one.isra.0': :(.text+0x7910): undefined reference to `__devm_regmap_init_i2c' drivers/pinctrl/built-in.o: In function `mcp23s08_init': :(.init.text+0x110): undefined reference to `i2c_register_driver' drivers/pinctrl/built-in.o: In function `mcp23s08_exit': :(.exit.text+0x3c): undefined reference to `i2c_del_driver' To avoid the problem, this adds another dependency on I2C that enforces mcp23s08 to be a loadable module whenever the I2C core is a module. Fixes: 64ac43e6 ("gpio: mcp23s08: move to pinctrl") Signed-off-by: NArnd Bergmann <arnd@arndb.de> Reviewed-by: NSebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 29 5月, 2017 1 次提交
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由 Linus Walleij 提交于
Fix compile errors due to missing OF. Cc: Paul Cercueil <paul@crapouillou.net> Reported-by: NRandy Dunlap <rdunlap@infradead.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 23 5月, 2017 3 次提交
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由 Sebastian Reichel 提交于
The driver compiles & works perfectly fine without OF_GPIO on x86, so lets drop the dependency. Signed-off-by: NSebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Sebastian Reichel 提交于
mcp23xxx device have configurable 100k pullup resistors. This adds support for enabling them using pinctrl's pinconf interface. Signed-off-by: NSebastian Reichel <sebastian.reichel@collabora.co.uk> Tested-by: NEnric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Sebastian Reichel 提交于
This moves the mcp23s08 driver from gpio to pinctrl. Actual pinctrl support for configuration of the pull-up resistors follows in its own patch. Signed-off-by: NSebastian Reichel <sebastian.reichel@collabora.co.uk> Acked-by: NSylvain Lemieux <slemieux.tyco@gmail.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 22 5月, 2017 2 次提交
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由 Paul Cercueil 提交于
This driver handles pin configuration and pin muxing for the JZ4740 and JZ4780 SoCs from Ingenic. Signed-off-by: NPaul Cercueil <paul@crapouillou.net> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Shawn Guo 提交于
The pin controller on ZTE ZX platforms is kinda of hybrid. It consists of a main controller and an auxiliary one. For example, on ZX296718 SoC, the main controller is TOP_PMM and the auxiliary one is AON_IOCFG. Both controllers work together to control pin multiplexing and configuration. For most of pins, the pinmux function is controlled by main controller only, and this type of pins are meant by term 'TOP pins'. For other pins, the pinmux is controlled by both main and auxiliary controllers, as the available multiplexing functions for the pin spread in both controllers. This type of pins are called 'AON pins'. Though pinmux implementation is quite different, pinconf is same for both types of pins. Both are controlled by auxiliary controller, i.e. AON_IOCFG on ZX296718. The patch adds the ZTE ZX core pinctrl driver to support this hybrid pin controller as well as ZX296718 SoC specific pin data. Signed-off-by: NShawn Guo <shawn.guo@linaro.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 07 4月, 2017 1 次提交
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由 Jesper Nilsson 提交于
Add pinctrl driver support for the Axis ARTPEC-6 SoC. There are only some pins that actually have different functions available, but all can control bias (pull-up/-down) and drive strength. Code originally written by Chris Paterson. Signed-off-by: NJesper Nilsson <jesper.nilsson@axis.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 10 1月, 2017 1 次提交
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由 Nishanth Menon 提交于
SoC family such as DRA7 family of processors have, in addition to the regular muxing of pins (as done by pinctrl-single), a separate hardware module called IODelay which is also expected to be configured. The "IODelay" module has it's own register space that is independent of the control module and the padconf register area. With recent changes to the pinctrl framework, we can now support this hardware with a reasonably minimal driver by using #pinctrl-cells, GENERIC_PINCTRL_GROUPS and GENERIC_PINMUX_FUNCTIONS. It is advocated strongly in TI's official documentation considering the existing design of the DRA7 family of processors during mux or IODelay reconfiguration, there is a potential for a significant glitch which may cause functional impairment to certain hardware. It is hence recommended to do as little of muxing as absolutely necessary without I/O isolation (which can only be done in initial stages of bootloader). NOTE: with the system wide I/O isolation scheme present in DRA7 SoC family, it is not reasonable to do stop all I/O operations for every such pad configuration scheme. So, we will let it glitch when used in this mode. Even with the above limitation, certain functionality such as MMC has mandatory need for IODelay reconfiguration requirements, depending on speed of transfer. In these cases, with careful examination of usecase involved, the expected glitch can be controlled such that it does not impact functionality. In short, IODelay module support as a padconf driver being introduced here is not expected to do SoC wide I/O Isolation and is meant for a limited subset of IODelay configuration requirements that need to be dynamic and whose glitchy behavior will not cause functionality failure for that interface. IMPORTANT NOTE: we take the approach of keeping LOCK_BITs cleared to 0x0 at all times, even when configuring Manual IO Timing Modes. This is done by eliminating the LOCK_BIT=1 setting from Step of the Manual IO timing Mode configuration procedure. This option leaves the CFG_* registers unprotected from unintended writes to the CTRL_CORE_PAD_* registers while Manual IO Timing Modes are configured. This approach is taken to allow for a generic driver to exist in kernel world that has to be used carefully in required usecases. Signed-off-by: NNishanth Menon <nm@ti.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> [tony@atomide.com: updated to use generic pinctrl functions, added binding documentation, updated comments] Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 03 1月, 2017 5 次提交
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由 Tony Lindgren 提交于
We can now drop the driver specific code for managing functions. Signed-off-by: NTony Lindgren <tony@atomide.com> [Replaces GENERIC_PINMUX with GENERIC_PINMUX_FUNCTIONS] Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Tony Lindgren 提交于
We can now drop the driver specific code for managing groups. Signed-off-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Tony Lindgren 提交于
We can add generic helpers for function handling for cases where the pin controller driver does not need to use static arrays. Signed-off-by: NTony Lindgren <tony@atomide.com> [Renamed the Kconfig item and moved things around] Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Linus Walleij 提交于
Rename the symbol PINCTRL_GENERIC to PINCTRL_GENERIC_GROUPS since it all pertains to groups. Replace everywhere. ifdef out the radix tree and the struct when not using the generic groups. Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Tony Lindgren 提交于
We can add generic helpers for pin group handling for cases where the pin controller driver does not need to use static arrays. Signed-off-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 07 12月, 2016 1 次提交
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由 David Lechner 提交于
This adds a new driver for pinconf on TI DA850/OMAP-L138/AM18XX. These SoCs have a separate controller for controlling pullup/pulldown groups. Signed-off-by: NDavid Lechner <david@lechnology.com> Reviewed-by: NSekhar Nori <nsekhar@ti.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 08 11月, 2016 1 次提交
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由 Andrey Smirnov 提交于
To allow for future code simplification Tested-by: NNeil Armstrong <narmstrong@baylibre.com> Acked-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NAndrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 29 10月, 2016 1 次提交
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由 Arnd Bergmann 提交于
Drivers using pinconf_generic_params tables cannot be built with CONFIG_OF disabled: drivers/pinctrl/pinctrl-max77620.c:53:44: error: array type has incomplete element type ‘struct pinconf_generic_params’ drivers/pinctrl/pinctrl-max77620.c:55:3: error: field name not in record or union initializer drivers/pinctrl/pinctrl-max77620.c:55:3: note: (near initialization for ‘max77620_cfg_params’) drivers/pinctrl/pinctrl-max77620.c:56:3: error: field name not in record or union initializer This adds a dependency for max77620 to disallow that configuration. Alternatively, we could rework the pinctrl infrastructure to make the configuration valid for compile-testing. Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Lee Jones <lee.jones@linaro.org> Fixes: 453943dc8f45 ("mfd: Enable compile testing for max77620 and max77686") Signed-off-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 24 10月, 2016 1 次提交
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由 Neil Armstrong 提交于
Since the I2C sx150x GPIO expander driver uses platform_data to manage the pins configurations, rewrite the driver as a pinctrl driver using pinconf to get/set pin configurations from DT or debugfs. The pinctrl driver is functionnally equivalent as the gpio-only driver and can use DT for pinconf. The platform_data confirmation is dropped. This patchset removed the gpio-only driver and selects the Pinctrl driver config instead. This patchset also migrates the gpio dt-bindings to pinctrl and add the pinctrl optional properties. The driver was tested with a SX1509 device on a BeagleBone black with interrupt support and on an X86_64 machine over an I2C to USB converter. This is a fixed version that builds and runs on non-OF platforms and on arm based OF. The GPIO version is removed and the bindings are also moved to the pinctrl bindings. Changes since v2 - rebased on v4.9-rc1 - removed MODULE_DEVICE_TABLE as in upstream bb411e77 ("gpio: sx150x: fix implicit assumption module.h is present") Changes since v1 - Fix Kconfig descriptions on pinctrl and gpio - Fix Kconfig dependency - Remove oscio support for non-789 devices - correct typo in dt bindings - remove probe reset for non-789 devices Changes since RFC - Put #ifdef CONFIG_OF/CONFIG_OF_GPIO to remove OF code for non-of platforms - No more rely on OF_GPIO config - Moved and enhanced bindings to pinctrl bindings - Removed gpio-sx150x.c - Temporary select PINCTRL_SX150X when GPIO_SX150X - Temporary mark GPIO_SX150X as deprecated Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Tested-by: NPeter Rosin <peda@axentia.se> Acked-by: NRob Herring <robh@kernel.org> ested-by: NAndrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 07 9月, 2016 1 次提交
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由 Andrew Jeffery 提交于
The Aspeed SoCs typically provide more than 200 pins for GPIO and other functions. The signal enabled on a pin is determined on a priority basis, where a given pin can provide a number of different signal types. In addition to the priority levels, the Aspeed pin controllers describe the signal active on a pin by compound logical expressions involving multiple operators, registers and bits. Some difficulty arises as a pin's function bit masks for each priority level are frequently not the same (i.e. we cannot just flip a bit to change from a high to low priority signal), or even in the same register(s). Some configuration bits affect multiple pins, while in other cases the signals for a bus must each be enabled individually. Together, these features give rise to some complexity in the implementation. A more complete description of the complexities is provided in the associated header file. The patch doesn't implement pinctrl/pinmux/pinconf for any particular Aspeed SoC, rather it adds the framework for defining pinmux configurations. Signed-off-by: NAndrew Jeffery <andrew@aj.id.au> Reviewed-by: NJoel Stanley <joel@jms.id.au> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 23 6月, 2016 2 次提交
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由 Paul Gortmaker 提交于
The Kconfig currently controlling compilation of this code is: config PINCTRL_AS3722 bool "Pinctrl and GPIO driver for ams AS3722 PMIC" ...meaning that it currently is not being built as a module by anyone. During an audit for non-modular drivers using modular infrastructure this driver showed up. But rather than demodularize it, Laxman indicated that it would be prefereable to instead convert the driver option to tristate. This does that, and confirms that it will compile and modpost as such. However, since I do not have the hardware to confirm that no new runtime issues exist when modular, that remains untested. Cc: Laxman Dewangan <ldewangan@nvidia.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Paul Gortmaker 提交于
The Kconfig currently controlling compilation of this code is: config PINCTRL_PALMAS bool "Pinctrl driver for the PALMAS Series MFD devices" ...meaning that it currently is not being built as a module by anyone. During an audit for non-modular drivers using modular infrastructure this driver showed up. But rather than demodularize it, Laxman indicated that it would be prefereable to instead convert the driver option to tristate. This does that, and confirms that it will compile and modpost as such. However, since I do not have the hardware to confirm that no new runtime issues exist when modular, that remains untested. Cc: Laxman Dewangan <ldewangan@nvidia.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 15 6月, 2016 1 次提交
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由 Arnd Bergmann 提交于
The recently added max77620 driver fails to build when CONFIG_PINMUX is not set: pinctrl/pinctrl-max77620.c:272:21: error: variable 'max77620_pinmux_ops' has initializer but incomplete type static const struct pinmux_ops max77620_pinmux_ops = { ^~~~~~~~~~ pinctrl/pinctrl-max77620.c:273:2: error: unknown field 'get_functions_count' specified in initializer This adds the Kconfig 'select' statement that was clearly meant to be there and is used in all other pinmux drivers. Signed-off-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 30 5月, 2016 2 次提交
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由 Laxman Dewangan 提交于
MAXIM Semiconductor's PMIC, MAX77620/MAX20024 has 8 GPIO pins which also act as the special function in alternate mode. Also there is configuration like push-pull, open drain, FPS timing etc for these pins. Add pin control driver to configure these parameters through pin control APIs. Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> Reviewed-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Neil Armstrong 提交于
Add pinctrl and gpio control support to Oxford Semiconductor OXNAS SoC Family. This version supports the ARM926EJ-S based OX810SE SoC with 34 IO pins. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 16 2月, 2016 1 次提交
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由 Jean Delvare 提交于
The pinctrl-amd driver builds just fine as a module so give users this option. Signed-off-by: NJean Delvare <jdelvare@suse.de> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 06 2月, 2016 1 次提交
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由 Joshua Henderson 提交于
Add a driver for the pin controller present on the Microchip PIC32 including the specific variant PIC32MZDA. This driver provides pinmux and pinconfig operations as well as GPIO and IRQ chips for the GPIO banks. Signed-off-by: NJoshua Henderson <joshua.henderson@microchip.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 05 2月, 2016 1 次提交
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由 Masahiro Yamada 提交于
Tegra has several pinctrl drivers. Now it is reasonable enough to move them into drivers/pinctrl/tegra/. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Acked-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 27 1月, 2016 1 次提交
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由 Maxime Coquelin 提交于
This patch adds pinctrl and GPIO support to STMicroelectronic's STM32 family of MCUs. While it only supports STM32F429 for now, it has been designed to enable support of other MCUs of the family (e.g. STM32F746). Acked-by: NPatrice Chotard <patrice.chotard@st.com> Signed-off-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 10 12月, 2015 1 次提交
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由 Robert Jarzmik 提交于
As the pxa architecture, at least for pxa27x, supports pin control, activate it in the pinctrl tree. Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 01 12月, 2015 1 次提交
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由 Masahiro Yamada 提交于
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 17 11月, 2015 1 次提交
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由 Masahiro Yamada 提交于
The whole menu is guarded by menu "Pin controllers" depends on PINCTRL ... endmenu The if conditional outside of it is redundant. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 22 9月, 2015 1 次提交
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由 Ludovic Desroches 提交于
Add a pinctrl/gpio driver for Atmel PIO4 controller available on SAMA5D2 chip family. Signed-off-by: NLudovic Desroches <ludovic.desroches@atmel.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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