Signed-off-by: NSaeed Bishara <saeed@marvell.com>
Signed-off-by: NNicolas Pitre <nico@fluxnic.net>

Add a kirkwood_nand_init_rnb() call to allow boards which
have RnB line detection to register this instead of a
static delay.
Signed-off-by: NBen Dooks <ben@simtec.co.uk>
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>

The (void *) cast is not needed when setting dev.platform_data to the
address of the data. Remove the casts.
Signed-off-by: NH Hartley Sweeten <hsweeten@visionengravers.com>
Cc: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: NNicolas Pitre <nico@marvell.com>

Disable propagation of mbus errors to the CPU local bus, as this causes
mbus errors (which can occur for example for PCI aborts) to throw CPU
aborts, which we're not set up to deal with.
Reported-by: NDieter Kiermaier <dk-arm-linux@gmx.de>
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
Signed-off-by: NNicolas Pitre <nico@marvell.com>

kirkwood_timer_init() and kirkwood_pcie_setup() lack of __init which
causes following warnings:

WARNING: vmlinux.o(.text+0x9568): Section mismatch in reference from
the function kirkwood_timer_init() to the function
.init.text:kirkwood_find_tclk()
The function kirkwood_timer_init() references
the function __init kirkwood_find_tclk().
This is often because kirkwood_timer_init lacks a __init
annotation or the annotation of kirkwood_find_tclk is wrong.

WARNING: vmlinux.o(.text+0x979c): Section mismatch in reference from
the function kirkwood_pcie_setup() to the function
.init.text:orion_pcie_setup()
The function kirkwood_pcie_setup() references
the function __init orion_pcie_setup().
This is often because kirkwood_pcie_setup lacks a __init
annotation or the annotation of orion_pcie_setup is wrong.
Signed-off-by: Nlijie <eltshanli@gmail.com>
Signed-off-by: NNicolas Pitre <nico@fluxnic.net>

Signed-off-by: NSiddarth Gore <gores@marvell.com>
Signed-off-by: NNicolas Pitre <nico@marvell.com>

Signed-off-by: NNicolas Pitre <nico@marvell.com>

The Orion watchdog driver is also used on Kirkwood.

Convention is to use orion5x for stuff specific to 88F5xxx Orion chips
and simply "orion" for shared stuff across SoCs including Kirkwood.
Signed-off-by: NNicolas Pitre <nico@marvell.com>

The Kirkwood architecture uses the same watchdog device as the Orion
architecture. This patch adds orion5x_wdt as a platform device for
Kirkwood.
Signed-off-by: NThomas Reitmayr <treitmayr@devbase.at>
Tested-by: NMartin Michlmayr <tbm@cyrius.com>
Signed-off-by: NNicolas Pitre <nico@marvell.com>

To save power:

1. Enabling clock gating of unused peripherals

2. PLL and PHY of the units are also disabled (when possible.
Signed-off-by: NRabeeh Khoury <rabeeh@marvell.com>
Signed-off-by: NNicolas Pitre <nico@marvell.com>

Common resource and platform device structures are moved to common.c
and only the partition table and chip delay remains a per board
parameter.
Signed-off-by: NNicolas Pitre <nico@marvell.com>

Since commit eb0519b5, mv643xx_eth is non functional on ARM because
the platform device declaration does not include any coherent DMA mask
and coherent memory allocations fail.
Signed-off-by: NNicolas Pitre <nico@marvell.com>

Remove explicit names from platform device resources since they will
automatically be named after the platform device they're associated
with.
Signed-off-by: NMartin Michlmayr <tbm@cyrius.com>
Acked-by: NRussell King <linux@arm.linux.org.uk>
Signed-off-by: NNicolas Pitre <nico@marvell.com>

Symbols like SOFT_RESET are way too generic to be exported at large.
To avoid this, let's move the mbus bridge register defines into a
separate file and include it where needed.  This affects mach-kirkwood,
mach-loki, mach-mv78xx0 and mach-orion5x simultaneously as they all
share code in plat-orion which relies on those defines.

Some other defines have been moved to narrower scopes, or simply deleted
when they had no user.

This fixes compilation problem with mpt2sas on the above listed
platforms.
Signed-off-by: NNicolas Pitre <nico@marvell.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Replace all DMA_32BIT_MASK macro with DMA_BIT_MASK(32)

Signed-off-by: Yang Hongyang<yanghy@cn.fujitsu.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Replace all DMA_64BIT_MASK macro with DMA_BIT_MASK(64)

Signed-off-by: Yang Hongyang<yanghy@cn.fujitsu.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Hook up I2C on Marvell Kirkwood.  Tested on a QNAP TS-219 which has
RTC connected through I2C.
Signed-off-by: NMartin Michlmayr <tbm@cyrius.com>
Signed-off-by: NNicolas Pitre <nico@marvell.com>

The initial version of the DSA driver only supported a single switch
chip per network interface, while DSA-capable switch chips can be
interconnected to form a tree of switch chips.  This patch adds support
for multiple switch chips on a network interface.

An example topology for a 16-port device with an embedded CPU is as
follows:

	+-----+          +--------+       +--------+
	|     |eth0    10| switch |9    10| switch |
	| CPU +----------+        +-------+        |
	|     |          | chip 0 |       | chip 1 |
	+-----+          +---++---+       +---++---+
	                     ||               ||
	                     ||               ||
	                     ||1000baseT      ||1000baseT
	                     ||ports 1-8      ||ports 9-16

This requires a couple of interdependent changes in the DSA layer:

- The dsa platform driver data needs to be extended: there is still
  only one netdevice per DSA driver instance (eth0 in the example
  above), but each of the switch chips in the tree needs its own
  mii_bus device pointer, MII management bus address, and port name
  array. (include/net/dsa.h)  The existing in-tree dsa users need
  some small changes to deal with this. (arch/arm)

- The DSA and Ethertype DSA tagging modules need to be extended to
  use the DSA device ID field on receive and demultiplex the packet
  accordingly, and fill in the DSA device ID field on transmit
  according to which switch chip the packet is heading to.
  (net/dsa/tag_{dsa,edsa}.c)

- The concept of "CPU port", which is the switch chip port that the
  CPU is connected to (port 10 on switch chip 0 in the example), needs
  to be extended with the concept of "upstream port", which is the
  port on the switch chip that will bring us one hop closer to the CPU
  (port 10 for both switch chips in the example above).

- The dsa platform data needs to specify which ports on which switch
  chips are links to other switch chips, so that we can enable DSA
  tagging mode on them.  (For inter-switch links, we always use
  non-EtherType DSA tagging, since it has lower overhead.  The CPU
  link uses dsa or edsa tagging depending on what the 'root' switch
  chip supports.)  This is done by specifying "dsa" for the given
  port in the port array.

- The dsa platform data needs to be extended with information on via
  which port to reach any given switch chip from any given switch chip.
  This info is specified via the per-switch chip data struct ->rtable[]
  array, which gives the nexthop ports for each of the other switches
  in the tree.

For the example topology above, the dsa platform data would look
something like this:

	static struct dsa_chip_data sw[2] = {
		{
			.mii_bus	= &foo,
			.sw_addr	= 1,
			.port_names[0]	= "p1",
			.port_names[1]	= "p2",
			.port_names[2]	= "p3",
			.port_names[3]	= "p4",
			.port_names[4]	= "p5",
			.port_names[5]	= "p6",
			.port_names[6]	= "p7",
			.port_names[7]	= "p8",
			.port_names[9]	= "dsa",
			.port_names[10]	= "cpu",
			.rtable		= (s8 []){ -1, 9, },
		}, {
			.mii_bus	= &foo,
			.sw_addr	= 2,
			.port_names[0]	= "p9",
			.port_names[1]	= "p10",
			.port_names[2]	= "p11",
			.port_names[3]	= "p12",
			.port_names[4]	= "p13",
			.port_names[5]	= "p14",
			.port_names[6]	= "p15",
			.port_names[7]	= "p16",
			.port_names[10]	= "dsa",
			.rtable		= (s8 []){ 10, -1, },
		},
	},

	static struct dsa_platform_data pd = {
		.netdev		= &foo,
		.nr_switches	= 2,
		.sw		= sw,
	};
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
Tested-by: NGary Thomas <gary@mlbassoc.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

The RTC and the two XOR engines are internal to the chip, and therefore
always available since they don't depend on a particular board layout.
Signed-off-by: NNicolas Pitre <nico@marvell.com>

Signed-off-by: NNicolas Pitre <nico@marvell.com>

Otherwise the mv643xx_eth driver will assume 133 MHz which is incorrect.
Signed-off-by: NNicolas Pitre <nico@marvell.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The 88f6192 and 88f6281 Kirkwood SoCs support two ethernet ports.
Add the platform glue that will allow board support files to
instantiate the second ethernet port.
Signed-off-by: NRonen Shitrit <rshitrit@marvell.com>
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
Signed-off-by: NNicolas Pitre <nico@marvell.com>

The Orion ehci driver serves the Orion, kirkwood and DD Soc families.
Since each of those integrate a different USB phy we should have the
ability to use few initialization sequences or to leave the boot loader
phy settings as is.
Signed-off-by: NRonen Shitrit <rshitrit@marvell.com>

This adds DSA switch instantiation hooks to the orion5x and the
kirkwood ARM SoC platform code, and instantiates the DSA switch
driver on the 88F5181L FXO RD, the 88F5181L GE RD, the 6183 AP GE
RD, the Linksys WRT350n v2, and the 88F6281 RD boards.
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
Tested-by: NNicolas Pitre <nico@marvell.com>
Tested-by: NPeter van Valderen <linux@ddcrew.com>
Tested-by: NDirk Teurlings <dirk@upexia.nl>
Signed-off-by: NNicolas Pitre <nico@marvell.com>

Feroceon L2 cache can work in eighther write through or write back mode
on Kirkwood. Add the option to configure this mode according to Kconfig.
Signed-off-by: NRonen Shitrit <rshitrit@marvell.com>
Signed-off-by: NNicolas Pitre <nico@marvell.com>

Add support to the Kirkwood port for newer device models and silicon
revisions.  Instead of looking at the DEVICE_ID register, the device
version is now determined by looking at the PCI-Express device ID and
revision registers, as it is done for orion5x, and this information
is used to determine the TCLK frequency, again, as it is done for
orion5x.
Signed-off-by: NRonen Shitrit <rshitrit@marvell.com>
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

Currently, kirkwood uses a hardcoded timer tick rate of 166 MHz, but
the actual timer tick rate varies between different members of the SoC
family.

This patch prepares for runtime determination of the timer tick rate.
Signed-off-by: NRonen Shitrit <rshitrit@marvell.com>

Wire up the ethernet port's error interrupt so that the
mv643xx_eth driver can sleep for SMI event completion instead of
having to busy-wait for it.
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

Signed-off-by: NSaeed Bishara <saeed@marvell.com>
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

This patch performs the equivalent include directory shuffle for
plat-orion, and fixes up all users.
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

This just leaves include/asm-arm/plat-* to deal with.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This patch allows booting Kirkwood with the L2 in writeback mode,
by reading the WT override bit from the L2 config register and
passing that into the Feroceon L2 init routine, instead of assuming
that the WT override bit will always be set
Signed-off-by: NSaeed Bishara <saeed@marvell.com>
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

The Marvell Kirkwood (88F6000) is a family of ARM SoCs based on a
Shiva CPU core, and features a DDR2 controller, a x1 PCIe interface,
a USB 2.0 interface, a SPI controller, a crypto accelerator, a TS
interface, and IDMA/XOR engines, and depending on the model, also
features one or two Gigabit Ethernet interfaces, two SATA II
interfaces, one or two TWSI interfaces, one or two UARTs, a
TDM/SLIC interface, a NAND controller, an I2S/SPDIF interface, and
an SDIO interface.

This patch adds supports for the Marvell DB-88F6281-BP Development
Board and the RD-88F6192-NAS and the RD-88F6281 Reference Designs,
enabling support for the PCIe interface, the USB interface, the
ethernet interfaces, the SATA interfaces, the TWSI interfaces, the
UARTs, and the NAND controller.
Signed-off-by: NSaeed Bishara <saeed@marvell.com>
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>