v2: update version for amd-staging-drm-next merge
Signed-off-by: NChunming Zhou <david1.zhou@amd.com>
Reviewed-by: NLionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

syncobj wait/signal operation is appending in command submission.
v2: separate to two kinds in/out_deps functions
v3: fix checking for timeline syncobj
Signed-off-by: NChunming Zhou <david1.zhou@amd.com>
Cc: Tobias Hector <Tobias.Hector@amd.com>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Cc: Dave Airlie <airlied@redhat.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: NLionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

- Fixes for powerplay custom profiles
- DC bandwidth clean ups and fixes
- RAS fixes for vega20
- DC atomic resume fix
- Better plane handling in DC
- Freesync improvements
- Misc bug fixes and cleanups
Signed-off-by: NDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190411031242.3337-1-alexander.deucher@amd.com

drm-misc-next for 5.2:

UAPI Changes:
- None

Cross-subsystem Changes:
-MAINTAINERS: Add moderation flag for lima mailing list (Randy)
-dt-bindings: Add Mali Bifrost bindings (Neil)
-dt-bindings: Add G12A compatibility strings to meson bindings (Neil)

Core Changes:
-Add a handful of format helpers (Gerd)

Driver Changes:
-cirrus: Driver rewrite megapatch (Gerd)
-meson: Add G12A support to meson driver (Neil)
-lima: Couple fixes (Qiang)

Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Randy Dunlap <rdunlap@infradead.org>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Qiang Yu <yuq825@gmail.com>
Signed-off-by: NDave Airlie <airlied@redhat.com>

From: Sean Paul <sean@poorly.run>
Link: https://patchwork.freedesktop.org/patch/msgid/20190410194907.GA108842@art_vandelay

Simply return true/false, don't iterate up the tree.
Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: NNikola Cornij <Nikola.Cornij@amd.com>
Acked-by: NLeo Li <sunpeng.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
When deciding to add properties or expose formats on DRM planes we
should be querying the caps for the DC plane it's supposed to represent.

[How]
Pass plane caps down into plane initialization, refactoring overlay
plane initialization to have the overlay plane be represented by
the first overlay capable DC plane.
Signed-off-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: NLeo Li <sunpeng.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]

dcn*_disable_plane() doesn't unlock the pipe anymore, making the extra
lock unnecessary.

In addition - during full plane updates - all necessary pipes should be
locked/unlocked together when modifying hubp to avoid tearing in
pipesplit setups.

[How]

Remove redundant locks, and add function to lock all pipes. If an
interdependent pipe update is required, lock down all pipes. Otherwise,
lock only the top pipe for the updated pipe tree.
Signed-off-by: NLeo Li <sunpeng.li@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]

When entering S3, amdgpu first calls DRM to cache the current atomic
state, then commit the 'all-disabled' state. This sets dc->current_state
to point at the private atomic object's dm_atomic_state->context, as
any regular atomic commit would.

Afterwards, amdgpu_dm calls dc_set_power_state() with S3 power state.
This invalidates dc->current_state by wiping it to 0, consequently
wiping dm_atomic_state->context.

During resume, the cached atomic state is restored. When getting the
private object however, the dm_atomic_state - containing the wiped
context - is duplicated into the atomic state. This causes DC validation
to fail during atomic check, as necessary function pointers in dc_state
are now NULL.

[How]

Recreate the private object's dm_atomic_state->context during resume,
restoring any static values such as function pointers.

A TODO item is added to move static read-only values out of dc_state -
they shouldn't be there anyways.
Signed-off-by: NLeo Li <sunpeng.li@amd.com>
Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Checking against a TF that is unused causes us to default to black

[How]
Check against PQ instead
Signed-off-by: NMurton Liu <murton.liu@amd.com>
Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NLeo Li <sunpeng.li@amd.com>
Acked-by: NTony Cheng <Tony.Cheng@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
New seamless boot sequence introduced a bug where front end is disabled
without blanking otg.

[How]
Adjust the condition of blanking otg to match seamless boot.
Signed-off-by: NEric Yang <Eric.Yang2@amd.com>
Reviewed-by: NAnthony Koo <Anthony.Koo@amd.com>
Acked-by: NLeo Li <sunpeng.li@amd.com>
Acked-by: NTony Cheng <Tony.Cheng@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
If link is already enabled at a different rate (for example 5.4 Gbps)
then calling VBIOS command table to switch to a new rate
(for example 2.7 Gbps) will not take effect.
This can lead to link training failure to occur.

[How]
If the requested link rate is different than the current link rate,
the link must be disabled in order to re-enable at the new
link rate.

In today's logic it is currently only impacting eDP since DP
connection types will always disable the link during display
detection, when initial link verification occurs.
Signed-off-by: NAnthony Koo <Anthony.Koo@amd.com>
Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NLeo Li <sunpeng.li@amd.com>
Acked-by: NTony Cheng <Tony.Cheng@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
In some cases we want DC init to take in some config options

[How]
Init dc_config before rest of DC init
Signed-off-by: NAnthony Koo <Anthony.Koo@amd.com>
Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NLeo Li <sunpeng.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
In HDR configurations, the cursor - in SDR - needs to have it's white
level boosted.

[How]
Program the cursor boost in update_dchubp_dpp like the other cursor
attributes.
Signed-off-by: NSivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com>
Reviewed-by: NAnthony Koo <Anthony.Koo@amd.com>
Acked-by: NLeo Li <sunpeng.li@amd.com>
Acked-by: NReza Amini <Reza.Amini@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
We need DC's color space to match the color encoding and color space
specified by userspace to correctly render YUV surfaces.

[How]
Convert the DRM color encoding and color range properties to the
appropriate DC colorspace option and update the color space when
performing surface updates.
Signed-off-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: NLeo Li <sunpeng.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
when preferred link cap is set, we should always use
preferred in all validation.
we should not use preferred for some validation but use
verified for others.

[how]
create getter function that gets verified link cap.
if preferred is set, return preferred link settings instead.
Signed-off-by: NWenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: NNikola Cornij <Nikola.Cornij@amd.com>
Acked-by: NLeo Li <sunpeng.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Image brightness compensation for solid color full screen images is
expected to be optimal for ABM 2.2 at level 3. The min reduction that is
currently being enforced prevents this from being achieved.

[How]
Remove the min reduction for ABM 2.2 at level 3
Signed-off-by: NJosip Pavic <Josip.Pavic@amd.com>
Reviewed-by: NAnthony Koo <Anthony.Koo@amd.com>
Acked-by: NLeo Li <sunpeng.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAric Cyr <aric.cyr@amd.com>
Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NLeo Li <sunpeng.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Before it was returning false in the case of failure even though return type should be enum dc_status

[How]
Return DC_FAIL_UNSUPPORTED_1 instead
Signed-off-by: NSu Sung Chung <Su.Chung@amd.com>
Reviewed-by: NEric Yang <eric.yang2@amd.com>
Acked-by: NLeo Li <sunpeng.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
The input color space for the plane was previously ignored even if it
was set.

If a limited range YUV format was given to DC then the
wrong color transformation matrix was being used since DC assumed that
it was full range instead.

[How]
Respect the given color_space format for the plane if it isn't
COLOR_SPACE_UNKNOWN. Otherwise, use the implicit default since DM
didn't specify.
Signed-off-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: NSun peng Li <Sunpeng.Li@amd.com>
Acked-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NLeo Li <sunpeng.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
Currently link bandwidth is calculated in two places, using the same
formula. They should be unified into calling one function.

[how]
Replace all implementations of link bandwidth calculation with a call
to a function.
Signed-off-by: NNikola Cornij <nikola.cornij@amd.com>
Reviewed-by: NNikola Cornij <Nikola.Cornij@amd.com>
Acked-by: NLeo Li <sunpeng.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

clk_mgr is called dccg in dc_state, this change fixes that
Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: NEric Bernstein <Eric.Bernstein@amd.com>
Acked-by: NLeo Li <sunpeng.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
The existing calculation uses a wrong formula to
calculate bandwidth from timing.

[how]
Expose the existing proper function that calculates the bandwidth,
so dc_link can use it to calculate timing bandwidth correctly.
Signed-off-by: NWenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: NJun Lei <Jun.Lei@amd.com>
Acked-by: NLeo Li <sunpeng.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
We are incorrectly using dp_hdmi_max_pixel_clk because the units are not clear.

[How]
Rename to dp_hdmi_max_pixel_clk_in_khz, and change mode timing validation to use
the value correctly.
Signed-off-by: NSivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com>
Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NLeo Li <sunpeng.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
DC provides a few visual confirmation debug options that can be
dynamically changed at runtime to help debug surface programming issues
but we don't have any way to access it from userspace.

[How]
Add the amdgpu_dm_visual_confirm debugfs entry.
It accepts a string containing the DC visual confirm enum value using
the debugfs attribute helpers.

The debugfs_create_file_unsafe can be used instead of
debugfs_create_file as per the documentation.

v2: Use debugfs helpers for getting and setting the value (Christian)

Cc: Leo Li <sunpeng.li@amd.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: NLeo Li <sunpeng.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

The brace initialization used here generates warnings on some
compilers. For example, on GCC 4.9:

[...] In function ‘dm_determine_update_type_for_commit’:
[...] error: missing braces around initializer [-Werror=missing-braces]
   struct dc_stream_update stream_update = { 0 };
          ^

Use memset to make this more portable.

v2: Specify the compiler / diagnostic in the commit message (Paul)

Cc: Sun peng Li <Sunpeng.Li@amd.com>
Cc: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: NLeo Li <sunpeng.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

The extra ; in the macro definition creates an empty statement
preventing any variable declarations from occuring after
any use of to_dm_plane_state(...).
Signed-off-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: NLeo Li <sunpeng.li@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Under vega10 virtualuzation, smu ip block will not be added.
Therefore, we need add pp clk query and force dpm level function
at amdgpu_virt_ops to support the feature.

v2: add get_pp_clk existence check and use kzalloc to allocate buf

v3: return -ENOMEM for allocation failure and correct the coding style
Signed-off-by: NYintian Tao <yttao@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

XGMI Memory sharing will be disbaled by default for security reason after
boot up, it depends on driver to enable the memory sharing
Signed-off-by: Nshaoyunl <shaoyun.liu@amd.com>
Acked-by: NEvan Quan <evan.quan@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

IP initialize ras in late_init, because of the BUGs of PSP or any
other components, driver receives unexpected irqs. It is ok to add such
check anyway.
Signed-off-by: Nxinhui pan <xinhui.pan@amd.com>
Reviewed-by: NEvan Quan <evan.quan@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

handle ras enable on boot.
Signed-off-by: Nxinhui pan <xinhui.pan@amd.com>
Reviewed-by: NEvan Quan <evan.quan@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

handle ras enable on boot.
Signed-off-by: Nxinhui pan <xinhui.pan@amd.com>
Reviewed-by: NEvan Quan <evan.quan@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

handle ras enable on boot.
Signed-off-by: Nxinhui pan <xinhui.pan@amd.com>
Reviewed-by: NEvan Quan <evan.quan@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Many parts of the whole SW stack can program the ras enablement state
during the boot. Now we handle that case by adding one function which
check the ras flags and choose different code path.
Reviewed-by: NEvan Quan <evan.quan@amd.com>
Signed-off-by: Nxinhui pan <xinhui.pan@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Unless IP has implemented its own ras, use ERROR_NONE as the default
type.
Signed-off-by: Nxinhui pan <xinhui.pan@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: NEvan Quan <evan.quan@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

use smu_update_table_with_arg to replace old code logic
Signed-off-by: NKevin Wang <kevin1.wang@amd.com>
Reviewed-by: NEvan Quan <evan.quan@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

in fact, the firmware need 2 parameter: 1.table_id, 2.XferArg
so change the function interface to match the firmware code
Signed-off-by: NKevin Wang <kevin1.wang@amd.com>
Reviewed-by: NEvan Quan <evan.quan@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

To prevent build fail on some platform which does
not have it in the include file chain.
Reviewed-by: NNeil Armstrong <narmstrong@baylibre.com>
Suggested-by: NRandy Dunlap <rdunlap@infradead.org>
Fixes: a1d2a633 ("drm/lima: driver for ARM Mali4xx GPUs")
Signed-off-by: NQiang Yu <yuq825@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190409003617.4470-2-yuq825@gmail.com

Current implementation does not support MMU-less
plarforms.
Suggested-by: NRandy Dunlap <rdunlap@infradead.org>
Reviewed-by: NNeil Armstrong <narmstrong@baylibre.com>
Fixes: a1d2a633 ("drm/lima: driver for ARM Mali4xx GPUs")
Signed-off-by: NQiang Yu <yuq825@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190409003617.4470-1-yuq825@gmail.com

The Amlogic G12A embeds the same Synopsys DW-HDMI Controller,
but with :
- a "backport" of the HDR signaling registers from more recent
  DW-HDMI controllers, this will need a tweak since it's not
  normally present on this version of the DW-HDMI controller
- A direct mapping of TOP and DW-HDMI registers instead of an
  internal bus accessed using read/write registers
- Support for RX-SENSE, but not yet implemented
- Support for HDMI 2.1 Dynamic HDR, but not yet implemented
- Different registers mapping for the HDMI PHY setup

This patchs adds support for these changes while providing exact
same support as the previous GXBB, GXL & GXM SoCs.
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Tested-by: NJerome Brunet <jbrunet@baylibre.com>
Reviewed-by: NJerome Brunet <jbrunet@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190325141824.21259-12-narmstrong@baylibre.com

Finally add the Amlogic G12A SoC compatible for the VPU driver.
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Tested-by: NJerome Brunet <jbrunet@baylibre.com>
Reviewed-by: NJerome Brunet <jbrunet@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190325141824.21259-11-narmstrong@baylibre.com