Device have SYS rail which is always ON. It is system power bus. LDO5
and LDO_RTC get powered through this rail internally. Add support for
this rail and make the LDO5/LDO_RTC supply by it. Update document
accordingly.

[swarren: Instantiate the sys regulator from board-harmony-power.c to
 avoid regression.]
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

Commit 3d55c29f "ARM: tegra: harmony: add regulator supply name and its
input supply" was supposed to fix all the problems with regulators on
Harmony. However, it appears that I only tested it when booting using
board files, not when booting using device tree. This change fixes two
problems with regulators when booting using device tree:

1) That patch only created the vdd_sys regulator when booting using a
   board file. Since this is the root of the whole regulator tree, this
   caused no regulators to successfully initialize when booting using
   device tree. The registration of vdd_sys is moved to fix this.

2) When booting use DT, the regulator core sets has_full_constraints,
   which in turn causes the core to turn off any regulators not marked
   as always on. Some of the affected regulators are required for basic
   system operation. To solve this, add always on constraints to all
   relevant regulators. This doesn't affect booting using a board file
   since nothing sets has_full_constraints in that case.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Name the regulator as per board schematics and adds its
supply name info in regulator data.
Add the always on fixed regulator to refer the battery supply.

Use this fixed regulator for input supply of some of PMIC
regulator

This patch was originally part of a 2-patch series. Patch 2 got applied
to the regulator tree as 7c7fac30 "regulator: tps6586x: add support for
input supply" without this patch. This broke regulator support on
Harmony.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
[swarren: added dependency info to commit description]
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Whistler is a highly configurable Tegra evaluation and development board.
This change adds support for the following specific configuration:

E1120 motherboard
E1108 CPU board
E1116 PMU board

The motherboard configuration switches are set as follows:
SW1=0 SW2=0 SW3=5
S1/S2/S3/S4 all on, except S3 7/8 are off.

Other combinations of daugher boards may work to varying degrees, but will
likely require some SW adjustment.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Use the dmaengine based Tegra APB DMA driver for
apbio access in place of legacy Tegra APB DMA.

The new driver is selected if legacy driver is not
selected and new DMA driver is enabled through config
file.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
[swarren: s/pr_err/pr_debug/ in tegra_apb_dma_init; this condition is
expected to fire repeatedly before the DMA driver is available]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The Tegra20 HW issue with accessing APBIO registers (such
as fuse registers) directly from the CPU concurrently with
APB DMA accesses has been fixed in Tegra30 and later chips.

Access these registers directly from the CPU on Tegra30
and later, and apply the workaround only for Tegra20.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Tested-by: NChaitanya Bandi <bandik@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

A subsequent patch will add a generic PWM API driver for the Tegra PWFM
controller, supporting all four PWM devices with a single PWM chip. The
device will be named tegra-pwm and only one clock needs to be provided.
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

PWM clock source registers in Tegra 2 have different clock source selection bit
fields than other registers.  PWM clock source bits in CLK_SOURCE_PWM_0 register
are located at bit field bit[30:28] while others are at bit field bit[31:30] in
their respective clock source register.

This patch updates the clock programming to correctly reflect that, by adding a
flag to indicate the alternate bit field format and checking for it when
selecting a clock source (parent clock).
Signed-off-by: NBill Huang <bilhuang@nvidia.com>
Signed-off-by: NSimon Que <sque@chromium.org>
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add auxdata to instantiate the PWFM controller from a device tree,
include the corresponding nodes in the dtsi files for Tegra 20 and
Tegra 30 and add binding documentation.
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>

of_default_bus_match_table is a table of default bus types supported by
of_platform_populate(). Since Tegra has no need to support any specific
custom list of bus types, modify the DT board files to use this default
list.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add DT AUXDATA for Tegra's APBDMA controller driver.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Rename the driver name of the clock entry of Tegra APBDMA to
tegra-apbdma from of tegra-dma.

This name is more aligned towards the movement of dmaengine based
new DMA driver.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

In Tegra30 clock file two clk objects were created for same UART clock.
Remove the duplicates and add clock aliases instead.

Update the Tegra20 clock file to make the names consistent.
Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

There currently aren't bindings for a WiFi rfkill button, and defining
a good binding is non-trivial. Manually register this "device" when
booting from device tree, in order to bring DT support to the same
feature level as board files, which will in turn allow board files to be
deprecated.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

There currently aren't bindings for the Tegra PCIe controller. Work on
this is in progress, but not yet complete. Manually initialize PCIe when
booting from device tree, in order to bring DT support to the same
feature level as board files, which will in turn allow board files to be
deprecated.

PCIe on Harmony requires various regulators to be registered and enabled
before initializing the PCIe controller. Note that since the I2C
controllers are instantiated from DT, we must use i2c_new_device() to
register the PMU rather than i2c_register_board_info().
Signed-off-by: NStephen Warren <swarren@nvidia.com>

There currently aren't bindings for the Tegra PCIe controller. Work on
this is in progress, but not yet complete. Manually initialize PCIe when
booting from device tree, in order to bring DT support to the same
feature level as board files, which will in turn allow board files to be
deprecated.

PCIe hosts the wired Ethernet controller on TrimSlice.

To support this, add infra-structure to board-dt-tegra20.c for board-
specific initialization code. Once device tree support for the relevant
features is in place, this code will be removed.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The Seaboard device tree supports all the features that the Seaboard
board files support. Hence, there's no need to keep the board files
around any more; all users should convert to device tree.

MACH_KAEN and MACH_WARIO are also removed. While tegra-seaboard.dts
doesn't support those explicitly, it would be trivial to create device
trees for those boards if anyone cares.

The Seaboard device tree is now compiled if Tegra2 support is enabled,
rather than when Seaboard support is enabled.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

* Make ARCH_TEGRA select USE_OF; DT is the way forward.
* Build board-dt-tegra*.c when the relevant Tegra SoC support is enabled,
  rather than requiring a specific config option for this.
* The board-specific config options already build board-*-pinmux.o, and
  when booting from device tree these files are no longer needed, so we
  can remove some Makefile commands related to those files.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Update Makefile.boot to compile *.dts when the appropriate Tegra SoC
support is enabled, rather than requiring Kconfig to list each board
individually. Remove CONFIG_MACH_VENTANA now that it has no use.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

powergate functions are needed for tegra30 as well (see common.c), so
build it always. Fixes:

arch/arm/mach-tegra/built-in.o: In function `tegra30_init_early':
apbio.c:(.init.text+0x78): undefined reference to `tegra_powergate_init'

(using "allnoconfig" with tegra30 enabled)
Signed-off-by: NWolfram Sang <w.sang@pengutronix.de>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Most ARM ${board}.dts files are already named ${soc}-${board}.dts. This
change modifies the Tegra board files to be named the same way for
consistency.

Once a related change is made in U-Boot, this will cause both U-Boot and
the kernel to use the same names for the .dts files and SoC identifiers,
thus allowing U-Boot's recently added "soc" and "board" environment
variables to be used to construct the name of Tegra .dtb files, and hence
allow board-generic U-Boot bootcmd scripts to be written.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

This solves a section mismatch warning. I hadn't noticed this before,
because my compiler was inlining tegra_cpu_reset_handler_enable() inside
tegra_cpu_reset_handler_init(), which is already __init, but I switched
compilers and it stopped doing that.

Cc: <stable@kernel.org> # v3.4
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Use clk_prepare/clk_unprepare as required by the generic clk framework.

Tested on Ventana and Cardhu.
Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The Tegra ASoC machine drivers only depend on Tegra architecture support
to compile, not specific board support. Remove Kconfig dependencies on
any particular board. This is required since Kconfig options for boards
are going away given the migration to device tree.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NMark Brown <broonie@opensource.wolfsonmicro.com>

This particular code had no effect on WFI execution. It only
asserts/de-asserts signal to tegra "legacy" CPU idle stats
monitor, which we are no longer using (cpufreq is based on
kernel s/w idle stats instead).
Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

flowctrl_write_cpu_csr uses the cpu halt offsets and vice versa. This patch
fixes this bug.
Reported-by: NDan Willemsen <dwillemsen@nvidia.com>
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
[swarren: This problem was introduced in v3.4-rc1, in commit 26fe681f "ARM:
 tegra: functions to access the flowcontroller", when this file was first
 added]
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Most PCI implementations use the standard PCI swizzle function, which
handles the well defined behaviour of PCI-to-PCI bridges which can be
found on cards (eg, four port ethernet cards.)

Rather than having almost every platform specify the standard swizzle
function, make this the default when no swizzle function is supplied.
Therefore, a swizzle function only needs to be provided when there is
something exceptional which needs to be handled.

This gets rid of the swizzle initializer from 47 files, and leaves us
with just two platforms specifying a swizzle function: ARM Integrator
and Chalice CATS.
Acked-by: NKrzysztof Hałasa <khc@pm.waw.pl>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

For bare minimal system.
Signed-off-by: NHiroshi DOYU <hdoyu@nvidia.com>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

For bare minimal system.
Signed-off-by: NHiroshi DOYU <hdoyu@nvidia.com>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Tegra Memory Controller(MC) driver for Tegra30
Added to support MC General interrupts, mainly for IOMMU(SMMU).
Signed-off-by: NHiroshi DOYU <hdoyu@nvidia.com>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Tegra Memory Controller(MC) driver for Tegra20
Added to support MC General interrupts, mainly for IOMMU(GART).
Signed-off-by: NHiroshi DOYU <hdoyu@nvidia.com>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Add extern func, "tegra_ahb_enable_smmu()" to inform AHB that SMMU is
ready.
Signed-off-by: NHiroshi DOYU <hdoyu@nvidia.com>
Cc: Felipe Balbi <balbi@ti.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Tegra AHB Bus conforms to the AMBA Specification (Rev 2.0) Advanced
High-performance Bus (AHB) architecture.

The AHB Arbiter controls AHB bus master arbitration. This effectively
forms a second level of arbitration for access to the memory
controller through the AHB Slave Memory device. The AHB pre-fetch
logic can be configured to enhance performance for devices doing
sequential access. Each AHB master is assigned to either the high or
low priority bin. Both Tegra20/30 have this AHB bus.

Some of configuration params could be passed from DT too if needed.
Signed-off-by: NHiroshi DOYU <hdoyu@nvidia.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Cc: Felipe Balbi <balbi@ti.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Cc: Colin Cross <ccross@android.com>
Cc: Olof Johansson <olof@lixom.net>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>

At the moment, read_persistent_clock is implemented at the
platform level, which makes it impossible to compile these
platforms in a single kernel.

Implement these two functions at the architecture level, and
provide a thin registration interface for both read_boot_clock
and read_persistent_clock. The two affected platforms (OMAP and
Tegra) are converted at the same time.
Reported-by: NJeff Ohlstein <johlstei@codeaurora.org>
Tested-by: NStephen Warren <swarren@wwwdotorg.org>
Tested-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Some SKUs limit the maximum CPU frequency to 750MHz; see
tegra2_pllx_clk_init(). The pll_x frequency table needs an entry for this
frequency, or there will be continual log spam from the cpufreq driver
attempting to set this rate, yet there being no table entry for it.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

ULPI PHYs have a reset signal, and different boards use a different GPIO
for this task. Add a property to device tree to represent this.

I'm not sure if adding this property to the EHCI controller node is
entirely correct; perhaps eventually we should have explicit separate
nodes for the various PHYs. However, we don't have that right now, so this
binding seems like a reasonable choice.

Cc: <devicetree-discuss@lists.ozlabs.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: <linux-usb@vger.kernel.org>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Not all boards use GPIO_PV0 as the ULPI PHY reset signal. Instead of
hard-coding this GPIO into devices.c, make the board files set it
explicitly. This will allow the PHY code to differentiate between set and
unset values, and hence know when to read the value from device tree.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

pll_p_out4 is used on all/most Tegra boards to drive the cdev2 output pin
to provide a reference clock to a ULPI USB PHY. This reference clock must
run at 24MHz, and the cdev2 output has no additional dividers.

Remove board-paz00.c's now-duplicate initialization of this clock.
Reported-by: NMarc Dietrich <marvin24@gmx.de>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Commit 40f9cf0 "ARM: tegra: reparent sclk to pll_c_out1" changed the
rate of hclk. Since pclk is derived from that, and only has integer
dividers, the pclk rate needs to change in the same fashion, from 54MHz
to 60MHz.
Signed-off-by: NStephen Warren <swarren@nvidia.com>