- 06 12月, 2011 1 次提交
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由 Will Deacon 提交于
The CPU reset functions disable the MMU and therefore must be executed with an identity mapping in place. This patch places the CPU reset functions into the .idmap.text section, causing the idmap code to include them as part of the identity mapping. Acked-by: NDave Martin <dave.martin@linaro.org> Signed-off-by: NWill Deacon <will.deacon@arm.com>
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- 07 7月, 2011 1 次提交
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由 Dave Martin 提交于
Signed-off-by: NDave Martin <dave.martin@linaro.org>
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- 23 2月, 2011 1 次提交
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由 Russell King 提交于
This adds core support for saving and restoring CPU coprocessor registers for suspend/resume support. This contains support for suspend with ARM920, ARM926, SA11x0, PXA25x, PXA27x, PXA3xx, V6 and V7 CPUs. Tested on Assabet and Tegra 2. Tested-by: NColin Cross <ccross@android.com> Tested-by: NKukjin Kim <kgene.kim@samsung.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 08 10月, 2010 1 次提交
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由 Russell King 提交于
When hotplug CPU is enabled, we need to keep the list of supported CPUs, their setup functions, and __lookup_processor_type in place so that we can find and initialize secondary CPUs. Move these into the __CPUINIT section. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 27 7月, 2010 1 次提交
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由 Russell King 提交于
All implementations of cpu_proc_fin() start by disabling interrupts and then flush caches. Rather than have every processors proc_fin() implementation do this, move it out into generic code - and move the cache flush past setup_mm_for_reboot() (so it can benefit from having caches still enabled.) This allows cpu_proc_fin() to become independent of the L1/L2 cache types, and eventually move the L2 cache flushing into the L2 support code. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 03 10月, 2009 1 次提交
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由 Kirill A. Shutemov 提交于
Instruction fault status register, IFSR, was introduced on ARMv6 to provide status information about the last insturction fault. It needed for proper prefetch abort handling. Now we have three prefetch abort model: * legacy - for CPUs before ARMv6. They doesn't provide neither IFSR nor IFAR. We simulate IFSR with section translation fault status for them to generalize code; * ARMv6 - provides IFSR, but not IFAR; * ARMv7 - provides both IFSR and IFAR. Signed-off-by: NKirill A. Shutemov <kirill@shutemov.name> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 25 3月, 2009 1 次提交
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由 Paulius Zaleckas 提交于
Adds support for Faraday FA526 core. This core is used at least by: Cortina Systems Gemini and Centroid family Cavium Networks ECONA family Grain Media GM8120 Pixelplus ImageARM Prolific PL-1029 Faraday IP evaluation boards v2: - move TLB_BTB to separate patch - update copyrights Signed-off-by: NPaulius Zaleckas <paulius.zaleckas@teltonika.lt>
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