- 28 5月, 2010 1 次提交
-
-
由 Matt Fleming 提交于
Even though many mmc host drivers pass a pm_message_t argument to mmc_suspend_host() that argument isn't used the by MMC core. As host drivers are converted to dev_pm_ops they'll have to construct pm_message_t's (as they won't be passed by the PM subsystem any more) just to appease the mmc suspend interface. We might as well just delete the unused paramter. Signed-off-by: NMatt Fleming <matt@console-pimps.org> Acked-by: NAnton Vorontsov <cbouatmailru@gmail.com> Acked-by: Michal Miroslaw <mirq-linux@rere.qmqm.pl>ZZ Acked-by: NSascha Sommer <saschasommer@freenet.de> Cc: <linux-mmc@vger.kernel.org> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
-
- 11 5月, 2010 1 次提交
-
-
由 Eric Miao 提交于
delay_detect in HZ is confusing, convert it to be millisecond based. And thus remove those unnecessary call to msecs_to_jiffies() at runtime for this field. Other constants are converted assuming HZ == 100, which are basically true for those platforms. The assignment in csb726.c was incorrect, and is fixed in this patch as a result. Signed-off-by: NEric Miao <eric.y.miao@gmail.com> Acked-by: NRobert Jarzmik <robert.jarzmik@free.fr> Acked-by: NMarc Zyngier <maz@misterjones.org> Acked-by: NMarek Vasut <marek.vasut@gmail.com> Acked-by: NMike Rapoport <mike@compulab.co.il> Acked-by: NDaniel Mack <daniel@caiaq.de>
-
- 30 3月, 2010 1 次提交
-
-
由 Tejun Heo 提交于
include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h percpu.h is included by sched.h and module.h and thus ends up being included when building most .c files. percpu.h includes slab.h which in turn includes gfp.h making everything defined by the two files universally available and complicating inclusion dependencies. percpu.h -> slab.h dependency is about to be removed. Prepare for this change by updating users of gfp and slab facilities include those headers directly instead of assuming availability. As this conversion needs to touch large number of source files, the following script is used as the basis of conversion. http://userweb.kernel.org/~tj/misc/slabh-sweep.py The script does the followings. * Scan files for gfp and slab usages and update includes such that only the necessary includes are there. ie. if only gfp is used, gfp.h, if slab is used, slab.h. * When the script inserts a new include, it looks at the include blocks and try to put the new include such that its order conforms to its surrounding. It's put in the include block which contains core kernel includes, in the same order that the rest are ordered - alphabetical, Christmas tree, rev-Xmas-tree or at the end if there doesn't seem to be any matching order. * If the script can't find a place to put a new include (mostly because the file doesn't have fitting include block), it prints out an error message indicating which .h file needs to be added to the file. The conversion was done in the following steps. 1. The initial automatic conversion of all .c files updated slightly over 4000 files, deleting around 700 includes and adding ~480 gfp.h and ~3000 slab.h inclusions. The script emitted errors for ~400 files. 2. Each error was manually checked. Some didn't need the inclusion, some needed manual addition while adding it to implementation .h or embedding .c file was more appropriate for others. This step added inclusions to around 150 files. 3. The script was run again and the output was compared to the edits from #2 to make sure no file was left behind. 4. Several build tests were done and a couple of problems were fixed. e.g. lib/decompress_*.c used malloc/free() wrappers around slab APIs requiring slab.h to be added manually. 5. The script was run on all .h files but without automatically editing them as sprinkling gfp.h and slab.h inclusions around .h files could easily lead to inclusion dependency hell. Most gfp.h inclusion directives were ignored as stuff from gfp.h was usually wildly available and often used in preprocessor macros. Each slab.h inclusion directive was examined and added manually as necessary. 6. percpu.h was updated not to include slab.h. 7. Build test were done on the following configurations and failures were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my distributed build env didn't work with gcov compiles) and a few more options had to be turned off depending on archs to make things build (like ipr on powerpc/64 which failed due to missing writeq). * x86 and x86_64 UP and SMP allmodconfig and a custom test config. * powerpc and powerpc64 SMP allmodconfig * sparc and sparc64 SMP allmodconfig * ia64 SMP allmodconfig * s390 SMP allmodconfig * alpha SMP allmodconfig * um on x86_64 SMP allmodconfig 8. percpu.h modifications were reverted so that it could be applied as a separate patch and serve as bisection point. Given the fact that I had only a couple of failures from tests on step 6, I'm fairly confident about the coverage of this conversion patch. If there is a breakage, it's likely to be something in one of the arch headers which should be easily discoverable easily on most builds of the specific arch. Signed-off-by: NTejun Heo <tj@kernel.org> Guess-its-ok-by: NChristoph Lameter <cl@linux-foundation.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
-
- 16 12月, 2009 1 次提交
-
-
由 Alexey Dobriyan 提交于
Signed-off-by: NAlexey Dobriyan <adobriyan@gmail.com> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
-
- 02 12月, 2009 1 次提交
-
-
由 Daniel Mack 提交于
mmc_remove_host() will cause the mmc core to switch off the bus power by eventually calling pxamci_set_ios(). This function uses the regulator or the GPIO which have been freed already. This causes the following Oops on module unload. [ 49.519649] Unable to handle kernel paging request at virtual address 30303a70 [ 49.526878] pgd = c7084000 [ 49.529563] [30303a70] *pgd=00000000 [ 49.533136] Internal error: Oops: 5 [#1] [ 49.537025] last sysfs file: /sys/devices/platform/pxa27x-ohci/usb1/1-1/1-1:1.0/host0/target0:0:0/0:0:0:0/scsi_level [ 49.547471] Modules linked in: pxamci(-) eeti_ts [ 49.552061] CPU: 0 Not tainted (2.6.32-rc8 #322) [ 49.557001] PC is at regulator_is_enabled+0x3c/0xbc [ 49.561846] LR is at regulator_is_enabled+0x30/0xbc [ 49.566691] pc : [<c01a2448>] lr : [<c01a243c>] psr: 60000013 [ 49.566702] sp : c7083e70 ip : 30303a30 fp : 00000000 [ 49.578093] r10: c705e200 r9 : c7082000 r8 : c705e2e0 [ 49.583280] r7 : c7061340 r6 : c7061340 r5 : c7083e70 r4 : 00000000 [ 49.589759] r3 : c04dc434 r2 : c04dc434 r1 : c03eecea r0 : 00000047 [ 49.596241] Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user [ 49.603329] Control: 0000397f Table: a7084018 DAC: 00000015 [ 49.609031] Process rmmod (pid: 1101, stack limit = 0xc7082278) [ 49.614908] Stack: (0xc7083e70 to 0xc7084000) [ 49.619238] 3e60: c7082000 c703c4f8 c705ea00 c04f4074 [ 49.627366] 3e80: 00000000 c705e3a0 ffffffff c0247ddc c70361a0 00000000 c705e3a0 ffffffff [ 49.635499] 3ea0: c705e200 bf006400 c78c4f00 c705e200 c705e3a0 ffffffff c705e200 ffffffff [ 49.643633] 3ec0: c04d8ac8 c02476d0 ffffffff c0247c60 c705e200 c0248678 c705e200 c0249064 [ 49.651765] 3ee0: ffffffff bf006204 c04d8ad0 c04d8ad0 c04d8ac8 bf007490 00000880 c00440c4 [ 49.659898] 3f00: 0000b748 c01c5708 bf007490 c01c44c8 c04d8ac8 c04d8afc bf007490 c01c4570 [ 49.668031] 3f20: bf007490 bf00750c c04f4258 c01c37a4 00000000 bf00750c c7083f44 c007b014 [ 49.676162] 3f40: 4000d000 6d617870 08006963 00000001 00000000 c7085000 00000001 00000000 [ 49.684287] 3f60: 4000d000 c7083f8c 00000001 bea01a54 00005401 c7ab1400 c00440c4 00082000 [ 49.692420] 3f80: bf00750c 00000880 c7083f8c 00000000 4000cfa8 00000000 00000880 bea01cc8 [ 49.700552] 3fa0: 00000081 c0043f40 00000000 00000880 bea01cc8 00000880 00000006 00000000 [ 49.708677] 3fc0: 00000000 00000880 bea01cc8 00000081 00000097 0000cca4 0000b748 00000000 [ 49.716802] 3fe0: 4001a4f0 bea01cc0 00018bf4 4001a4fc 20000010 bea01cc8 a063e021 a063e421 [ 49.724958] [<c01a2448>] (regulator_is_enabled+0x3c/0xbc) from [<c0247ddc>] (mmc_regulator_set_ocr+0x14/0xd8) [ 49.734836] [<c0247ddc>] (mmc_regulator_set_ocr+0x14/0xd8) from [<bf006400>] (pxamci_set_ios+0xd8/0x17c [pxamci]) [ 49.745044] [<bf006400>] (pxamci_set_ios+0xd8/0x17c [pxamci]) from [<c02476d0>] (mmc_power_off+0x50/0x58) [ 49.754555] [<c02476d0>] (mmc_power_off+0x50/0x58) from [<c0247c60>] (mmc_detach_bus+0x68/0xc4) [ 49.763207] [<c0247c60>] (mmc_detach_bus+0x68/0xc4) from [<c0248678>] (mmc_stop_host+0xd4/0x1bc) [ 49.771944] [<c0248678>] (mmc_stop_host+0xd4/0x1bc) from [<c0249064>] (mmc_remove_host+0xc/0x20) [ 49.780681] [<c0249064>] (mmc_remove_host+0xc/0x20) from [<bf006204>] (pxamci_remove+0xc8/0x174 [pxamci]) [ 49.790211] [<bf006204>] (pxamci_remove+0xc8/0x174 [pxamci]) from [<c01c5708>] (platform_drv_remove+0x1c/0x24) [ 49.800164] [<c01c5708>] (platform_drv_remove+0x1c/0x24) from [<c01c44c8>] (__device_release_driver+0x7c/0xc4) [ 49.810110] [<c01c44c8>] (__device_release_driver+0x7c/0xc4) from [<c01c4570>] (driver_detach+0x60/0x8c) [ 49.819535] [<c01c4570>] (driver_detach+0x60/0x8c) from [<c01c37a4>] (bus_remove_driver+0x90/0xcc) [ 49.828452] [<c01c37a4>] (bus_remove_driver+0x90/0xcc) from [<c007b014>] (sys_delete_module+0x1d8/0x254) [ 49.837891] [<c007b014>] (sys_delete_module+0x1d8/0x254) from [<c0043f40>] (ret_fast_syscall+0x0/0x28) [ 49.847145] Code: eb06c53a e596c030 e1a0500d e59f106c (e59c0040) [ 49.853566] ---[ end trace b5fa66a00cea142f ]--- Signed-off-by: NDaniel Mack <daniel@caiaq.de> Reported-by: NSven Neumann <s.neumann@raumfeld.com> Cc: Pierre Ossman <pierre@ossman.eu> Cc: linux-mmc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: stable@kernel.org Signed-off-by: NEric Miao <eric.y.miao@gmail.com>
-
- 01 12月, 2009 1 次提交
-
-
由 Haojian Zhuang 提交于
Along with more processor supporting 26MHz mode (including pxa935), introduce an individual macro mmc_has_26mhz() for this. Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: NEric Miao <eric.y.miao@gmail.com>
-
- 12 10月, 2009 1 次提交
-
-
由 Antonio Ospite 提交于
Signed-off-by: NAntonio Ospite <ospite@studenti.unina.it> Reviewed-by: NRobert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: NEric Miao <eric.y.miao@gmail.com>
-
- 10 9月, 2009 2 次提交
-
-
由 Mike Rapoport 提交于
Signed-off-by: NMike Rapoport <mike@compulab.co.il> Signed-off-by: NEric Miao <eric.y.miao@gmail.com>
-
由 Robert Jarzmik 提交于
The MMC block needs 3 external datas to work : - is the MMC card put in "read-only mode" ? - is a MMC card inserted or removed ? - enable power towards the MMC card Several platforms provide these controls through gpios. Expand the platform_data to request and use these gpios is set up by board code. Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr> Acked-by: NPierre.Ossman <pierre@ossman.eu> Signed-off-by: NEric Miao <eric.y.miao@gmail.com>
-
- 03 7月, 2009 1 次提交
-
-
由 Matt Reimer 提交于
The DMA flow control in pxamci_setup_data() is backwards; fix it. Signed-off-by: NMatt Reimer <mreimer@sdgsystems.com> Acked-by: NRobert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: NEric Miao <eric.y.miao@gmail.com>
-
- 14 6月, 2009 1 次提交
-
-
由 Daniel Ribeiro 提交于
Changes pxamci.c to use the regulator subsystem. Uses the regulator case CONFIG_REGULATOR is defined and a matching is regulator is provided, or falls back to pdata->setpower otherwise. A warning is displayed case both a valid regulator and pdata is set, and the regulator is used. Signed-off-by: NDaniel Ribeiro <drwyrm@gmail.com> Acked-by: NEric Miao <eric.miao@marvell.com> Signed-off-by: NPierre Ossman <pierre@ossman.eu>
-
- 09 3月, 2009 1 次提交
-
-
由 Eric Miao 提交于
1. Driver code where pxa_request_dma() is called will most likely reference DMA registers as well, and it is really unnecessary to include pxa-regs.h just for this. Move the definitions into <mach/dma.h> and make relevant drivers include it instead of <mach/pxa-regs.h>. 2. Introduce DMAC_REGS_VIRT as the virtual address base for these DMA registers. This allows later processors to re-use the same IP while registers may start at different I/O address. Signed-off-by: NEric Miao <eric.miao@marvell.com>
-
- 03 2月, 2009 2 次提交
-
-
由 Cliff Brake 提交于
With the PXA270 MMC hardware, there seems to be an issue of data corruption on writes where a 4KB data block is offset by one byte. If we delay enabling the DMA for writes until after the CMD/RESP has finished, the problem seems to be fixed. related to PXA270 Erratum #91 Tested-by: NVernon Sauder <VernonInHand@gmail.com> Signed-off-by: NCliff Brake <cbrake@bec-systems.com> Acked-by: NEric Miao <eric.miao@marvell.com> Signed-off-by: NPierre Ossman <drzeus@drzeus.cx>
-
由 Cliff Brake 提交于
Signed-off-by: NCliff Brake <cbrake@bec-systems.com> Acked-by: NEric Miao <eric.miao@marvell.com> Signed-off-by: NPierre Ossman <drzeus@drzeus.cx>
-
- 01 1月, 2009 1 次提交
-
-
由 Vernon Sauder 提交于
dma_unmap_sg should be given the same length as dma_map_sg, not the value returned from dma_map_sg Signed-off-by: NVernon Sauder <vsauder@inhand.com> Signed-off-by: NPierre Ossman <drzeus@drzeus.cx>
-
- 30 11月, 2008 1 次提交
-
-
由 Russell King 提交于
When ISA_DMA_API is unset, we're not implementing the ISA DMA API, so there's no point in publishing the prototypes via asm/dma.h, nor including the machine dependent parts of that API. This allows us to remove a lot of mach/dma.h files which don't contain any useful code. Unfortunately though, some platforms put their own private non-ISA definitions into mach/dma.h, so we leave these behind and fix the appropriate #include statments. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
-
- 29 11月, 2008 1 次提交
-
-
由 Russell King 提交于
Avoid unnecessarily pollution of the kernel's namespace by avoiding mach/hardware.h. Include this header file where necessary. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
-
- 27 11月, 2008 1 次提交
-
-
由 Russell King 提交于
Where devices only have one consumer, passing a consumer clock ID has no real benefit. Remove it. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
-
- 25 9月, 2008 1 次提交
-
-
由 Eric Miao 提交于
1. add a CPUID table in the comment 2. make cpu_is_pxa25x() true for PXA210/250/255/26x 3. PXA210 is treated as PXA25x, all related code modified to reflect this Signed-off-by: NEric Miao <eric.miao@marvell.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
-
- 07 8月, 2008 1 次提交
-
-
由 Russell King 提交于
This just leaves include/asm-arm/plat-* to deal with. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
-
- 23 7月, 2008 1 次提交
-
-
由 Karl Beldan 提交于
Signed-off-by: NKarl Beldan <karl.beldan@gmail.com> Acked-by: NEric Miao <eric.miao@marvell.com> Signed-off-by: NPierre Ossman <drzeus@drzeus.cx>
-
- 15 7月, 2008 1 次提交
-
-
由 Anton Vorontsov 提交于
Now get_ro() callback must return 0/1 values for its logical states, and negative errno values in case of error. If particular host instance doesn't support RO/WP switch, it should return -ENOSYS. This patch changes some hosts in two ways: 1. Now functions should be smart to not return negative values in "RO asserted" case (particularly gpio_ calls could return negative values for the outermost GPIOs). Also, board code usually passes get_ro() callbacks that directly return gpioreg & bit result, so at91_mci, imxmmc, pxamci and mmc_spi's get_ro() handlers need take special care when returning platform's values to the mmc core. 2. In case of host instance didn't implement get_ro() callback, it should really return -ENOSYS and let the mmc core decide what to do about it (mmc core thinks the same way as the hosts, so it isn't functional change). Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: NPierre Ossman <drzeus@drzeus.cx>
-
- 07 7月, 2008 1 次提交
-
-
由 Philipp Zabel 提交于
The pxa27x DMA controller defaults to 64-bit alignment. This caused the SCR reads to fail (and, depending on card type, error out) when card->raw_scr was not aligned on a 8-byte boundary. For performance reasons all scatter-gather addresses passed to pxamci_request should be aligned on 8-byte boundaries, but if this can't be guaranteed, byte aligned DMA transfers in the have to be enabled in the controller to get correct behaviour. Signed-off-by: NPhilipp Zabel <philipp.zabel@gmail.com> Signed-off-by: NPierre Ossman <drzeus@drzeus.cx> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
-
- 16 4月, 2008 1 次提交
-
-
由 Kay Sievers 提交于
Since 43cc71ee, the platform modalias is prefixed with "platform:". Add MODULE_ALIAS() to the hotpluggable MMC host platform drivers, to re-enable auto loading. Also, add missing owner declarations in driver init. [dbrownell@users.sourceforge.net: registration fixes] Signed-off-by: NKay Sievers <kay.sievers@vrfy.org> Signed-off-by: NDavid Brownell <dbrownell@users.sourceforge.net> Acked-by: NPierre Ossman <drzeus@drzeus.cx> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
-
- 26 1月, 2008 2 次提交
-
-
由 Bridge Wu 提交于
This patch is to move pxamci DMA specific code to corresponding platform layer because using DRCMRRXMMC/DRCMRTXMMC in pxamci.c makes the driver code dedicated to platform which is not extensible. It is applicable to all pxa platforms. Signed-off-by: NBridge Wu <bridge.wu@marvell.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
-
由 Bridge Wu 提交于
pxa3[0|1]0 mmc controller can support 26MHz clock mode, they support SD spec 1.1 and MMC spec 4.0 which specify high speed mode. So host caps will include MMC_CAP_MMC_HIGHSPEED and MMC_CAP_SD_HIGHSPEED for pxa3[0|1]0. This patch is to add 26MHz support for them. pxa host clock will be set to 26MHz mode when the card supported max clock rate is higher than or equal to 26MHz. Signed-off-by: NBridge Wu <bridge.wu@marvell.com> Acked-by: NPierre Ossman <drzeus@drzeus.cx> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
-
- 31 10月, 2007 1 次提交
-
-
由 Russell King 提交于
Fix: WARNING: at arch/arm/mach-pxa/clock.c:69 clk_disable() [<c002d7c8>] (dump_stack+0x0/0x14) from [<c00334f4>] (clk_disable+0x34/0xa0) [<c00334c0>] (clk_disable+0x0/0xa0) from [<c028a43c>] (pxamci_set_ios+0x74/0xf0) [<c028a3c8>] (pxamci_set_ios+0x0/0xf0) from [<c0281548>] (mmc_power_off+0x90/0x9c) [<c02814b8>] (mmc_power_off+0x0/0x9c) from [<c0281a30>] (mmc_start_host+0x18/0x28) [<c0281a18>] (mmc_start_host+0x0/0x28) from [<c02825a0>] (mmc_add_host+0xe8/0x104) [<c02824b8>] (mmc_add_host+0x0/0x104) from [<c028a7d0>] (pxamci_probe+0x24c/0x2f4) [<c028a584>] (pxamci_probe+0x0/0x2f4) from [<c01e5948>] (platform_drv_probe+0x20/0x24) ... Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
-
- 24 10月, 2007 1 次提交
-
-
由 Jens Axboe 提交于
Do a full scan of the directory to try and be a bit more proactive, instead of waiting for things to break. Signed-off-by: NJens Axboe <jens.axboe@oracle.com>
-
- 13 10月, 2007 1 次提交
-
-
由 Russell King 提交于
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
-
- 11 10月, 2007 1 次提交
-
-
由 Nicolas Pitre 提交于
The PXA has two transmit FIFOes, each32 byte deep. when one FIFO is full and the other one has been transmitted, they are automatically swapped and DMA is triggered for another 32 byte burst. However, when there is less than 32 bytes left to send, the FIFO swap has to be done manually. This is required for some SDIO transfers which are not required to be multiples of 32 bytes. A DMA completion interrupt is set for each descriptor which length isn't a multiple of 32 in order to force the FIFO swap. While at it, the DMA interrupt handler has been made a bit more resilient against errors. Signed-off-by: NNicolas Pitre <nico@marvell.com> Signed-off-by: NPierre Ossman <drzeus@drzeus.cx>
-
- 26 9月, 2007 4 次提交
-
-
由 Bridge Wu 提交于
Again, only available from PXA27x. Signed-off-by: NBridge Wu <mingqiao.wu@gmail.com> Signed-off-by: NNicolas Pitre <nico@marvell.com> Signed-off-by: NPierre Ossman <drzeus@drzeus.cx>
-
由 Bridge Wu 提交于
From PXA27x, it is possible to do 4-bit data transfers. Signed-off-by: NBridge Wu <mingqiao.wu@gmail.com> Signed-off-by: NNicolas Pitre <nico@marvell.com> Signed-off-by: NPierre Ossman <drzeus@drzeus.cx>
-
由 Nicolas Pitre 提交于
From PXA27x, it is possible to do 2048-byte block transfers. Signed-off-by: NNicolas Pitre <nico@marvell.com> Signed-off-by: NPierre Ossman <drzeus@drzeus.cx>
-
由 Bridge Wu 提交于
Pending interrupts should be determined from both I_REG and I_MASK registers. Signed-off-by: NBridge Wu <mingqiao.wu@gmail.com> Signed-off-by: NNicolas Pitre <nico@marvell.com> Signed-off-by: NPierre Ossman <drzeus@drzeus.cx>
-
- 23 9月, 2007 1 次提交
-
-
由 Pierre Ossman 提交于
Convert the MMC layer to use standard error codes and not its own, incompatible values. Signed-off-by: NPierre Ossman <drzeus@drzeus.cx>
-
- 26 7月, 2007 1 次提交
-
-
由 Pierre Ossman 提交于
Make sure all headers in the files reflect their true position in the tree. Signed-off-by: NPierre Ossman <drzeus@drzeus.cx>
-
- 15 5月, 2007 1 次提交
-
-
由 Nicolas Pitre 提交于
... and make it depend on the response flag instead of the command type. Signed-off-by: NNicolas Pitre <npitre@mvista.com> Signed-off-by: NPierre Ossman <drzeus@drzeus.cx>
-
- 01 5月, 2007 2 次提交
-
-
由 Pierre Ossman 提交于
Clean up the drivers/mmc directory by moving card and host drivers into subdirectories. Signed-off-by: NPierre Ossman <drzeus@drzeus.cx>
-
由 Pierre Ossman 提交于
All host drivers were #include:ing mmc/protocol.h just to get access to the OCR bit defines. Move these to host.h instead. Signed-off-by: NPierre Ossman <drzeus@drzeus.cx>
-
- 22 4月, 2007 1 次提交
-
-
由 Eric Miao 提交于
This patch removes the unnecessary bit number from CKENnn_XXXX definitions for PXA, so that CKEN0_PWM0 --> CKEN_PWM0 CKEN1_PWM1 --> CKEN_PWM1 ... CKEN24_CAMERA --> CKEN_CAMERA The reasons for the change of these defitions are: 1. they do not scale - they are currently valid for pxa2xx, but definitely not valid for pxa3xx, e.g., pxa3xx has bit 3 for camera instead of bit 24 2. they are unnecessary - the peripheral name within the definition has already announced its usage, we don't need those bit numbers to know which peripheral we are going to enable/disable clock for 3. they are inconvenient - think about this: a driver programmer for pxa has to remember which bit in the CKEN register to turn on/off Another change in the patch is to make the definitions equal to its clock bit index, so that #define CKEN_CAMERA (24) instead of #define CKEN_CAMERA (1 << 24) this change, however, will add a run-time bit shift operation in pxa_set_cken(), but the benefit of this change is that it scales when bit index exceeds 32, e.g., pxa3xx has two registers CKENA and CKENB, totally 64 bit for this, suppose CAMERA clock enabling bit is CKENB:10, one can simply define CKEN_CAMERA to be (32 + 10) and so that pxa_set_cken() need minimum change to adapt to that. Signed-off-by: Neric miao <eric.y.miao@gmail.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
-