1. 28 4月, 2016 1 次提交
    • V
      drm/i915: Update RAWCLK_FREQ register on VLV/CHV · 19ab4ed3
      Ville Syrjälä 提交于
      I just noticed that VLV/CHV have a RAWCLK_FREQ register just like PCH
      platforms. It lives in the display power well, so we should update it
      when enabling the power well.
      
      Interestingly the BIOS seems to leave it at the reset value (125) which
      doesn't match the rawclk frequency on VLV/CHV (200 MHz). As always with
      these register, the spec is extremely vague what the register does. All
      it says is: "This is used to generate a divided down clock for
      miscellaneous timers in display." Based on a quick test, at least AUX
      and PWM appear to be unaffected by this.
      
      But since the register is there, let's configure it in accordance with
      the spec.
      
      Note that we have to move intel_update_rawclk() to occur before we
      touch the power wells, so that the dev_priv->rawclk_freq is already
      populated when the disp2 enable hook gets called for the first time.
      I think this should be safe to do on other platforms as well.
      
      Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1461768202-17544-1-git-send-email-ville.syrjala@linux.intel.comReviewed-by: NRodrigo Vivi <rodrigo.vivi@intel.com>
      19ab4ed3
  2. 19 4月, 2016 1 次提交
    • J
      drm/i915: Clean up PCI config register handling · e10fa551
      Joonas Lahtinen 提交于
      Do not use magic numbers, do not prefix stuff with "PCI_", do not
      declare registers in implementation files. Also move the PCI
      registers under correct comment in i915_reg.h.
      
      v2:
      - Consistently use BSM (not BDSM or other variants from PRM) (Chris)
      - Also include register address to help identify the register (Chris)
      v3:
      - Refer to register value as *_val instead of *_reg (Chris)
      v4:
      - Make style checker happy
      
      Cc: Jani Nikula <jani.nikula@intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: NJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      e10fa551
  3. 01 4月, 2016 1 次提交
  4. 31 3月, 2016 1 次提交
    • J
      drm/i915: Refer to GGTT {,VM} consistently · 72e96d64
      Joonas Lahtinen 提交于
      Refer to the GGTT VM consistently as "ggtt->base" instead of just "ggtt",
      "vm" or indirectly through other variables like "dev_priv->ggtt.base"
      to avoid confusion with the i915_ggtt object itself and PPGTT VMs.
      
      Refer to the GGTT as "ggtt" instead of indirectly through chaining.
      
      As a bonus gets rid of the long-standing i915_obj_to_ggtt vs.
      i915_gem_obj_to_ggtt conflict, due to removal of i915_obj_to_ggtt!
      
      v2:
      - Added some more after grepping sources with Chris
      
      v3:
      - Refer to GGTT VM through ggtt->base consistently instead of ggtt_vm
        (Chris)
      
      v4:
      - Convert all dev_priv->ggtt->foo accesses to ggtt->foo.
      
      v5:
      - Make patch checker happy
      
      Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
      Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: NJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
      72e96d64
  5. 30 3月, 2016 2 次提交
  6. 23 3月, 2016 1 次提交
  7. 22 3月, 2016 1 次提交
  8. 18 3月, 2016 2 次提交
  9. 17 3月, 2016 19 次提交
  10. 16 3月, 2016 2 次提交
  11. 02 3月, 2016 1 次提交
  12. 01 3月, 2016 1 次提交
    • M
      drm/i915: Add two-stage ILK-style watermark programming (v11) · ed4a6a7c
      Matt Roper 提交于
      In addition to calculating final watermarks, let's also pre-calculate a
      set of intermediate watermark values at atomic check time.  These
      intermediate watermarks are a combination of the watermarks for the old
      state and the new state; they should satisfy the requirements of both
      states which means they can be programmed immediately when we commit the
      atomic state (without waiting for a vblank).  Once the vblank does
      happen, we can then re-program watermarks to the more optimal final
      value.
      
      v2: Significant rebasing/rewriting.
      
      v3:
       - Move 'need_postvbl_update' flag to CRTC state (Daniel)
       - Don't forget to check intermediate watermark values for validity
         (Maarten)
       - Don't due async watermark optimization; just do it at the end of the
         atomic transaction, after waiting for vblanks.  We do want it to be
         async eventually, but adding that now will cause more trouble for
         Maarten's in-progress work.  (Maarten)
       - Don't allocate space in crtc_state for intermediate watermarks on
         platforms that don't need it (gen9+).
       - Move WaCxSRDisabledForSpriteScaling:ivb into intel_begin_crtc_commit
         now that ilk_update_wm is gone.
      
      v4:
       - Add a wm_mutex to cover updates to intel_crtc->active and the
         need_postvbl_update flag.  Since we don't have async yet it isn't
         terribly important yet, but might as well add it now.
       - Change interface to program watermarks.  Platforms will now expose
         .initial_watermarks() and .optimize_watermarks() functions to do
         watermark programming.  These should lock wm_mutex, copy the
         appropriate state values into intel_crtc->active, and then call
         the internal program watermarks function.
      
      v5:
       - Skip intermediate watermark calculation/check during initial hardware
         readout since we don't trust the existing HW values (and don't have
         valid values of our own yet).
       - Don't try to call .optimize_watermarks() on platforms that don't have
         atomic watermarks yet.  (Maarten)
      
      v6:
       - Rebase
      
      v7:
       - Further rebase
      
      v8:
       - A few minor indentation and line length fixes
      
      v9:
       - Yet another rebase since Maarten's patches reworked a bunch of the
         code (wm_pre, wm_post, etc.) that this was previously based on.
      
      v10:
       - Move wm_mutex to dev_priv to protect against racing commits against
         disjoint CRTC sets. (Maarten)
       - Drop unnecessary clearing of cstate->wm.need_postvbl_update (Maarten)
      
      v11:
       - Now that we've moved to atomic watermark updates, make sure we call
         the proper function to program watermarks in
         {ironlake,haswell}_crtc_enable(); the failure to do so on the
         previous patch iteration led to us not actually programming the
         watermarks before turning on the CRTC, which was the cause of the
         underruns that the CI system was seeing.
       - Fix inverted logic for determining when to optimize watermarks.  We
         were needlessly optimizing when the intermediate/optimal values were
         the same (harmless), but not actually optimizing when they differed
         (also harmless, but wasteful from a power/bandwidth perspective).
      
      Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
      Signed-off-by: NMatt Roper <matthew.d.roper@intel.com>
      Reviewed-by: NMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1456276813-5689-1-git-send-email-matthew.d.roper@intel.com
      ed4a6a7c
  13. 15 2月, 2016 1 次提交
    • D
      Revert "drm/i915: fix context/engine cleanup order" · 1ffedc06
      Daniel Vetter 提交于
      This reverts commit 1b39a917.
      
      Chris retracted his reviewed-by (which I failed to notice) and somehow
      it blows up (I did it again!) as reported by Mika with the below
      backtrace on module reload:
      
      [   58.170374] IP: [<ffffffffa00e04d3>]
      intel_logical_ring_cleanup+0x83/0x100 [i915]
      ...
      [   58.170469] Call Trace:
      [   58.170479]  [<ffffffffa00d0ed4>] i915_gem_cleanup_engines+0x34/0x60
      [i915]
      [   58.170493]  [<ffffffffa0154520>] i915_driver_unload+0x140/0x220
      [i915]
      [   58.170497]  [<ffffffff8154a4f4>] drm_dev_unregister+0x24/0xa0
      [   58.170501]  [<ffffffff8154aace>] drm_put_dev+0x1e/0x60
      [   58.170506]  [<ffffffffa00912a0>] i915_pci_remove+0x10/0x20 [i915]
      [   58.170510]  [<ffffffff814766e4>] pci_device_remove+0x34/0xb0
      [   58.170514]  [<ffffffff8156e7d5>] __device_release_driver+0x95/0x140
      [   58.170518]  [<ffffffff8156e97c>] driver_detach+0xbc/0xc0
      [   58.170521]  [<ffffffff8156d883>] bus_remove_driver+0x53/0xd0
      [   58.170525]  [<ffffffff8156f3a7>] driver_unregister+0x27/0x50
      [   58.170528]  [<ffffffff81475725>] pci_unregister_driver+0x25/0x70
      [   58.170531]  [<ffffffff8154c274>] drm_pci_exit+0x74/0x90
      [   58.170543]  [<ffffffffa0154cb0>] i915_exit+0x20/0x1aa [i915]
      [   58.170548]  [<ffffffff8111846f>] SyS_delete_module+0x18f/0x1f0
      
      Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Dave Gordon <david.s.gordon@intel.com>
      Cc: Nick Hoath <nicholas.hoath@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@intel.com>
      1ffedc06
  14. 10 2月, 2016 2 次提交
  15. 08 2月, 2016 1 次提交
  16. 03 2月, 2016 1 次提交
  17. 02 2月, 2016 1 次提交
  18. 27 1月, 2016 1 次提交