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  1. 30 5月, 2014 12 次提交
  3. 28 5月, 2014 11 次提交
    • P
      MIPS: cpuidle wait instruction state · da9f970f
      由 Paul Burton 提交于 
      Defines a macro intended to allow trivial use of the regular MIPS wait
instruction from cpuidle drivers, which may simply invoke the macro
within their array of states.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      da9f970f
    • P
      MIPS: pm-cps: add PM state entry code for CPS systems · 3179d37e
      由 Paul Burton 提交于 
      This patch adds code to generate entry & exit code for various low power
states available on systems based around the MIPS Coherent Processing
System architecture (ie. those with a Coherence Manager, Global
Interrupt Controller & for >=CM2 a Cluster Power Controller). States
supported are:

  - Non-coherent wait. This state first leaves the coherent domain and
    then executes a regular MIPS wait instruction. Power savings are
    found from the elimination of coherency interventions between the
    core and any other coherent requestors in the system.

  - Clock gated. This state leaves the coherent domain and then gates
    the clock input to the core. This removes all dynamic power from the
    core but leaves the core at the mercy of another to restart its
    clock. Register state is preserved, but the core can not service
    interrupts whilst its clock is gated.

  - Power gated. This deepest state removes all power input to the core.
    All register state is lost and the core will restart execution from
    its BEV when another core powers it back up. Because register state
    is lost this state requires cooperation with the CONFIG_MIPS_CPS SMP
    implementation in order for the core to exit the state successfully.

The code will detect which states are available on the current system
during boot & generate the entry/exit code for those states. This will
be used by cpuidle & hotplug implementations.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      3179d37e
    • P
      MIPS: smp-cps: function to determine whether CPS SMP is in use · 68c1232f
      由 Paul Burton 提交于 
      The core power down state for cpuidle will require that the CPS SMP
implementation is in use. This patch provides a mips_cps_smp_in_use
function which determines whether or not the CPS SMP implementation is
currently in use.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      68c1232f
    • P
      MIPS: smp-cps: rework core/VPE initialisation · 245a7868
      由 Paul Burton 提交于 
      When hotplug and/or a powered down idle state are supported cases will
arise where a non-zero VPE must be brought online without VPE 0, and it
where multiple VPEs must be onlined simultaneously. This patch prepares
for that by:

  - Splitting struct boot_config into core & VPE boot config structures,
    allocated one per core or VPE respectively. This allows for multiple
    VPEs to be onlined simultaneously without clobbering each others
    configuration.

  - Indicating which VPEs should be online within a core at any given
    time using a bitmap. This allows multiple VPEs to be brought online
    simultaneously and also indicates to VPE 0 whether it should halt
    after starting any non-zero VPEs that should be online within the
    core. For example if all VPEs within a core are offlined via hotplug
    and the user onlines the second VPE within that core:

      1) The core will be powered up.

      2) VPE 0 will run from the BEV (ie. mips_cps_core_entry) to
         initialise the core.

      3) VPE 0 will start VPE 1 because its bit is set in the cores
         bitmap.

      4) VPE 0 will halt itself because its bit is clear in the cores
         bitmap.

  - Moving the core & VPE initialisation to assembly code which does not
    make any use of the stack. This is because if a non-zero VPE is to
    be brought online in a powered down core then when VPE 0 of that
    core runs it may not have a valid stack, and even if it did then
    it's messy to run through parts of generic kernel code on VPE 0
    before starting the correct VPE.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      245a7868
    • P
      MIPS: uasm: add MT ASE yield instruction · d674dd14
      由 Paul Burton 提交于 
      This patch allows use of the MT ASE yield instruction from uasm. It will
be used by a subsequent patch.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      d674dd14
    • P
      MIPS: uasm: add wait instruction · 53ed1389
      由 Paul Burton 提交于 
      This patch allows use of the wait instruction from uasm. It will be used
by a subsequent patch.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      53ed1389
    • P
      MIPS: uasm: add sync instruction · 729ff561
      由 Paul Burton 提交于 
      This patch allows use of the sync instruction from uasm. It will be used
by a subsequent patch.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      729ff561
    • P
      MIPS: uasm: add jalr instruction · 49e9529b
      由 Paul Burton 提交于 
      This patch allows use of the jalr instruction from uasm. It will be used
by a subsequent patch.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      49e9529b
    • P
      MIPS: uasm: add a label variant of beq · 8dee5901
      由 Paul Burton 提交于 
      This patch allows for use of the beq instruction with labels from uasm,
much as bne & others already do. It will be used by a subsequent patch.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      8dee5901
    • P
      MIPS: MT: define write_c0_tchalt macro · 27476f3b
      由 Paul Burton 提交于 
      Define a macro to write to the current TCs TCHalt register. This will be
used by a subsequent patch.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      27476f3b
    • P
      MIPS: add kmap_noncoherent to wire a cached non-coherent TLB entry · e2a9e5ad
      由 Paul Burton 提交于 
      This is identical to kmap_coherent apart from the cache coherency
attribute used for the TLB entry, so kmap_coherent is abstracted to
kmap_prot which is then called for both kmap_coherent &
kmap_noncoherent. This will be used by a subsequent patch.
Suggested-by: NLeonid Yegoshin <leonid.yegoshin@imgtec.com>
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      e2a9e5ad
  5. 27 5月, 2014 1 次提交
  7. 24 5月, 2014 1 次提交
    • R
      MIPS: MT: Remove SMTC support · b633648c
      由 Ralf Baechle 提交于 
      Nobody is maintaining SMTC anymore and there also seems to be no userbase.
Which is a pity - the SMTC technology primarily developed by Kevin D.
Kissell <kevink@paralogos.com> is an ingenious demonstration for the MT
ASE's power and elegance.

Based on Markos Chandras <Markos.Chandras@imgtec.com> patch
https://patchwork.linux-mips.org/patch/6719/ which while very similar did
no longer apply cleanly when I tried to merge it plus some additional
post-SMTC cleanup - SMTC was a feature as tricky to remove as it was to
merge once upon a time.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      b633648c
  9. 23 5月, 2014 9 次提交
  11. 21 5月, 2014 3 次提交
  13. 14 5月, 2014 1 次提交
  15. 13 5月, 2014 2 次提交
    • R
      MIPS: Remove file missed when removing rm9k support a while ago. · cdbb03b0
      由 Ralf Baechle 提交于 
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      cdbb03b0
    • M
      MIPS: DEC/SNI: O32 wrapper stack switching fixes · 824122a3
      由 Maciej W. Rozycki 提交于 
      Commit 231a35d3 [[MIPS] RM: Collected
changes] broke DECstation support by introducing an incompatible copy of
arch/mips/dec/prom/call_o32.S in arch/mips/fw/lib/, built unconditionally.
The copy happens to land earlier of the two among the modules used in the
link and is therefore chosen for the DECstation rather than the intended
original.  As a result random kernel data is corrupted because a pointer
to the "%s" formatted output template is used as a temporary stack pointer
rather than being passed down to prom_printf.  This also explains why
prom_printf still works, up to a point -- the next argument is the actual
string to output so it works just fine as the output template until enough
kernel data has been corrupted to cause a crash.

This change adjusts the modified wrapper in arch/mips/fw/lib/call_o32.S to
let callers request no stack switching by passing a null temporary stack
pointer in $a1, reworks the DECstation callers to work with the updated
interface and removes the old copy from arch/mips/dec/prom/call_o32.S.  A
few minor readability adjustments are included as well, most importantly
O32_SZREG is now used throughout where applicable rather than hardcoded
multiplies of 4 and $fp is used to access the argument save area as a more
usual register to operate the stack with rather than $s0.

Finally an update is made to the temporary stack space used by the SNI
platform to guarantee 8-byte alignment as per o32 requirements.
Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6668/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      824122a3