1. 09 7月, 2020 2 次提交
    • M
      bnxt_en: Add logical RSS indirection table structure. · 1667cbf6
      Michael Chan 提交于
      The driver currently does not keep track of the logical RSS indirection
      table.  The hardware RSS table is set up with standard default ring
      distribution when initializing the chip.  This makes it difficult to
      support user sepcified indirection table entries.  As a first step, add
      the logical table in the main bnxt structure and allocate it according
      to chip specific table size.  Add a function that sets up default
      RSS distribution based on the number of RX rings.
      
      v4: Use bnxt_get_rxfh_indir_size() for the current RSS table size.
      
      v2: Use kmalloc_array() since we init. all entries afterwards.
          Use ALIGN() to roundup the RSS table size.
          Use ethtool_rxfh_indir_default() to init. the default entries.
      Signed-off-by: NMichael Chan <michael.chan@broadcom.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      1667cbf6
    • M
      bnxt_en: Set up the chip specific RSS table size. · 34370d24
      Michael Chan 提交于
      Currently, we allocate one page for the hardware DMA RSS indirection
      table.  While the size is currently big enough for all chips, future
      chip variations may support bigger sizes, so it is better to calculate
      and store the chip specific size and allocate accordingly.
      Signed-off-by: NMichael Chan <michael.chan@broadcom.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      34370d24
  2. 24 6月, 2020 4 次提交
  3. 16 6月, 2020 4 次提交
  4. 27 5月, 2020 2 次提交
  5. 05 5月, 2020 6 次提交
  6. 28 4月, 2020 3 次提交
  7. 28 3月, 2020 2 次提交
  8. 24 3月, 2020 4 次提交
  9. 09 3月, 2020 8 次提交
  10. 06 3月, 2020 1 次提交
    • J
      bnxt_en: Use pci_get_dsn() · 8d85b75b
      Jacob Keller 提交于
      Replace the open-coded implementation for reading the PCIe DSN with
      pci_get_dsn().
      
      Use of put_unaligned_le64 should be correct. pci_get_dsn() will perform
      two pci_read_config_dword calls. The first dword will be placed in the
      first 32 bits of the u64, while the second dword will be placed in the
      upper 32 bits of the u64.
      
      On Little Endian systems, the least significant byte comes first, which
      will be the least significant byte of the first dword, followed by the
      least significant byte of the second dword. Since the _le32 variations
      do not perform byte swapping, we will correctly copy the dwords into the
      dsn[] array in the same order as before.
      
      On Big Endian systems, the most significant byte of the second dword
      will come first. put_unaligned_le64 will perform a CPU_TO_LE64, which
      will swap things correctly before copying. This should also end up with
      the correct bytes in the dsn[] array.
      
      While at it, fix a small typo in the netdev_info error message when the
      DSN cannot be read.
      Signed-off-by: NJacob Keller <jacob.e.keller@intel.com>
      Cc: Michael Chan <michael.chan@broadcom.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      8d85b75b
  11. 04 3月, 2020 1 次提交
  12. 02 3月, 2020 1 次提交
  13. 27 2月, 2020 1 次提交
  14. 21 2月, 2020 1 次提交