- 20 3月, 2014 3 次提交
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由 Jean-Jacques Hiblot 提交于
Signed-off-by: NBoris BREZILLON <b.brezillon@overkiz.com> Signed-off-by: NJean-Jacques Hiblot <jjhiblot@traphandler.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Jean-Jacques Hiblot 提交于
The PCKRDY bit is not set until the system clock is enabled. This patch moves the management of the ready status in the system clock driver. Signed-off-by: NBoris BREZILLON <b.brezillon@overkiz.com> Signed-off-by: NJean-Jacques Hiblot <jjhiblot@traphandler.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Boris BREZILLON 提交于
Implement the determine_rate callback to choose the best parent clk that fulfills the requested rate. Signed-off-by: NBoris BREZILLON <b.brezillon@overkiz.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 02 12月, 2013 1 次提交
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由 Boris BREZILLON 提交于
This patch adds new at91 programmable clocks implementation using common clk framework. A programmable clock is a clock which can be exported on a given pin to clock external devices. Each programmable clock is given an id (from 0 to 8). The number of available programmable clocks depends on the SoC you're using. Programmable clock driver only implements the clock setting (clock rate and parent setting). It must be chained to a system clock in order to enable/disable the generated clock. The PCKX pins used to output the clock signals must be assigned to the appropriate peripheral (see atmel's datasheets). Signed-off-by: NBoris BREZILLON <b.brezillon@overkiz.com> Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
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