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  1. 29 6月, 2018 1 次提交
  3. 08 1月, 2018 3 次提交
  5. 18 12月, 2017 7 次提交
  7. 17 9月, 2017 1 次提交
  9. 05 9月, 2017 1 次提交
  11. 14 3月, 2017 2 次提交
    • A
      dmaengine: xilinx: avoid memory corruption for device_prep_dma_memcpy() · db6a3d03
      由 Akinobu Mita 提交于 
      The device_prep_dma_memcpy() callback for this driver allocates a new
xilinx_dma_tx_descriptor whose TX segments list is initialized as empty,
but then gets invalid TX segment pointer by list_last_entry() from the
empty TX segments list and memory corruption happens by the attempt to
update the next descriptor in invalid TX segment pointer.

This removes unnecessary memory access for nonexistent tail TX segment
which causes memory corruption.

Cc: Vinod Koul <vinod.koul@intel.com>
Cc: Kedareswara rao Appana <appana.durga.rao@xilinx.com>
Cc: Michal Simek <monstr@monstr.eu>
Signed-off-by: NAkinobu Mita <akinobu.mita@gmail.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>
      db6a3d03
    • A
      dmaengine: xilinx: fix device_terminate_all() callback for AXI CDMA · 676f9c26
      由 Akinobu Mita 提交于 
      The device_terminate_all() callback for this driver stops current DMA
operations by clearing RUNSTOP bit in the control register and waiting
HALTED bit set in the status register.

But AXI CDMA which is one of the supported DMA engine by this driver
does not provide the run / stop controls and those bits in the control
and status registers are reserved.  So when device_terminate_all() is
called, the error message is printed and the channel is marked as having
errors in xilinx_dma_halt().

This change adds stop_transfer() callback which differentiates CDMA and
other DMA engine.  The CDMA's one avoids the unsupported operations and
instead polls the status register to check if the DMA operations are in
progress for AXI CDMA.

Cc: Vinod Koul <vinod.koul@intel.com>
Cc: Kedareswara rao Appana <appana.durga.rao@xilinx.com>
Cc: Michal Simek <monstr@monstr.eu>
Signed-off-by: NAkinobu Mita <akinobu.mita@gmail.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>
      676f9c26
  13. 08 8月, 2016 1 次提交
  15. 12 7月, 2016 1 次提交
  17. 08 7月, 2016 3 次提交
  19. 21 6月, 2016 2 次提交
    • K
      dmaengine: vdma: Add 64 bit addressing support for the axi cdma · 9791e71a
      由 Kedareswara rao Appana 提交于 
      The AXI CDMA is a soft ip, which can be programmed to support
32 bit addressing or greater than 32 bit addressing.

When the AXI CDMA ip is configured for 32 bit address space
in simple dma mode the source/destination buffer address is
specified by a single register(18h for Source buffer address and
20h for Destination buffer address). When configured in SG mode
the current descriptor and tail descriptor are specified by a
Single register(08h for curdesc 10h for tail desc).

When the  AXI CDMA core is configured for an address space greater
than 32 then each buffer address or descriptor address is specified by
a combination of two registers.

The first register specifies the LSB 32 bits of address,
while the next register specifies the MSB 32 bits of address.

For example, 08h will specify the LSB 32 bits while 0Ch will
specify the MSB 32 bits of the first start address.
So we need to program two registers at a time.

This patch adds the 64 bit addressing support to the axicdma
IP in the driver.
Signed-off-by: NKedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>
      9791e71a
    • K
      dmaengine: vdma: Add 64 bit addressing support for the axi dma · f0cba685
      由 Kedareswara rao Appana 提交于 
      The AXI DMA is a soft ip, which can be programmed to support
32 bit addressing or greater than 32 bit addressing.

When the AXI DMA ip is configured for 32 bit address space
in simple dma mode the buffer address is specified by a single register
(18h for MM2S channel and 48h for S2MM channel). When configured in SG mode
The current descriptor and tail descriptor are specified by a single
Register(08h for curdesc 10h for tail desc for MM2S channel and 38h for
Curdesc and 40h for tail desc for S2MM).

When the  AXI DMA core is configured for an address space greater
than 32 then each buffer address or descriptor address is specified by
a combination of two registers.

The first register specifies the LSB 32 bits of address,
while the next register specifies the MSB 32 bits of address.

For example, 48h will specify the LSB 32 bits while 4Ch will
specify the MSB 32 bits of the first start address.
So we need to program two registers at a time.

This patch adds the 64 bit addressing support for the axidma
IP in the driver.
Signed-off-by: NKedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>
      f0cba685
  21. 14 6月, 2016 1 次提交
    • A
      dmaengine: xilinx-vdma: add some sanity checks · f67c3bda
      由 Arnd Bergmann 提交于 
      The newly added xilinx_dma_prep_dma_cyclic function sometimes causes
a gcc warning about the use of the segment function in case
we never run into the inner loop of the function:

dma/xilinx/xilinx_vdma.c: In function 'xilinx_dma_prep_dma_cyclic':
dma/xilinx/xilinx_vdma.c:1808:23: error: 'segment' may be used uninitialized in this function [-Werror=maybe-uninitialized]
   segment->hw.control |= XILINX_DMA_BD_SOP;

This can only happen if the period len is zero (which would cause other
problems earlier), or if the buffer is shorter than a period. Neither
of them should ever happen, but by adding an explicit check for these two
cases, we can abort in a more controlled way, and the compiler is
able to see that we never use uninitialized data.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>
      f67c3bda
  23. 13 6月, 2016 1 次提交
  25. 07 6月, 2016 2 次提交
  27. 13 5月, 2016 2 次提交
  29. 12 5月, 2016 3 次提交
  31. 03 5月, 2016 1 次提交
  33. 06 4月, 2016 4 次提交
  35. 04 3月, 2016 1 次提交
  37. 03 3月, 2016 3 次提交